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CCS/TMS320VC5502: how to read Analog signal in TMS320VC5502

Part Number: TMS320VC5502
Other Parts Discussed in Thread: TMS320VC5501

Tool/software: Code Composer Studio

Hi,

     I refer C5502 Datasheet, there is no ADC pins. I want to read Analog signal (FSK caller id detection)in my project. I have customized C5502 board(in DSP5502 development board codec ic used to receive and transmit analog signal by using McBsp). Without Mcbsp and Codec ic , can i read analog signal in anyother method??

if anyother links??

share with me

Thanks 

  • Hi,

    The analog signal needs to be sampled outside of the C5502 and transferred digitally through McBSP, EMIF, or SPI (through McBSP).

    I should add that other C55x devices like C5505, C5515, C5535, C5545, C5517 have an on-chip SAR ADC that can sample upto 64 ksps.

    Hope this helps,
    Mark

  • Hi,

       How to read and Write PCM signal(32-channel) by using McBsp .(i refer CSL Example code , that code write16 bit or write 32 bit format, I cant clearly understand that concept)

    (In spru433j, Channel enable and Channel disable ,channel status only explained, No explanation about channel data read & write)

    In Mcbsp , clk is 2MHz & Frame Sync signal is 8-khz(0.125ms once high)

    PCM signal (32-channel) information from other system, i will give to McBsp Data Receive pin. i want to read particular channel information. After processing i want to Transmit particular channel information to other system..

    if any other sample code regarding interfacing PCM signal to McBsp (Read and write channel information), share with me

    Thanks

  • Hi,

    Is the PCM signal time-division multiplexed (are there 32 channels tranmitted serially between frame sync pulses?)

    Configuration of the McBSP for N channels is documented in TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide
    www.ti.com/.../spru592
    5.1 Channels, Blocks, and Partitions
    5.3 Configuring a Frame for Multichannel Selection
    7.2 Programming McBSP Registers for Desired Receiver Operation
    8.2 Programming McBSP Registers for Desired Transmitter Operation
    13 McBSP Register Worksheet

    Example code for the C5502 eZdsp shows the McBSP configuration for a 2-channel stream.
    support.spectrumdigital.com/.../
    See ezdsp5502_BSL_RevC.zip\ezdsp5502_v1\lib\bsl\ezdsp5502_mcbsp.c
    You can leverage this structure for your 32 channel stream.


    Maybe this thread will offer confidence that it is possible.
    e2e.ti.com/.../2328268

    Useful wiki:
    http://processors.wiki.ti.com/index.php/McASP_Tips

    Regards,
    Mark

  • Hi

     I wrote program  Mcbsp (Transmit program)32 channel . here, i write data to particular (0th & 31st channel)channel in McBsp whenever Frame SYNC interrupt occur. In Output , sometimes only data write in particular channel is successfully . most of time the data is not properly write to particular channel.here, i attach my code

    #include <stdio.h>
    #include <csl.h>
    #include <csl_pll.h>
    #include <csl_chip.h>
    #include <csl_irq.h>
    
    #include <csl_mcbsp.h>
    
    
    MCBSP_Handle McBsp0;
    #define CHANNEL 128
    
    extern void VECSTART(void);
    
    Uint16 EventId0,EventId1;
    long int Counter;
    Uint32 data,r,x;
    Uint32 i=0,data1,rdata[CHANNEL],xdata[CHANNEL],read,cap;
    unsigned char status,status1;
    
    MCBSP_Config ConfigLoopBack32= {
      MCBSP_SPCR1_RMK(
    	MCBSP_SPCR1_DLB_OFF,                    /* DLB    = 1 */
    	MCBSP_SPCR1_RJUST_RZF,                 /* RJUST  = 0 */
    	MCBSP_SPCR1_CLKSTP_DISABLE,            /* CLKSTP = 0 */
    	MCBSP_SPCR1_DXENA_NA,                  /* DXENA  = 0 */
    	MCBSP_SPCR1_ABIS_DISABLE,              /* ABIS   = 0 */
    	MCBSP_SPCR1_RINTM_FRM,                /* RINTM  = 0 */
    	0,                                     /* RSYNCERR = 0 */
    	MCBSP_SPCR1_RRST_DISABLE               /* RRST   = 0 */
       ),
        MCBSP_SPCR2_RMK(
        MCBSP_SPCR2_FREE_NO,                   /* FREE   = 0 */
        MCBSP_SPCR2_SOFT_NO,                   /* SOFT   = 0 */
        MCBSP_SPCR2_FRST_RESET,                /* FRST   = 0 */
        MCBSP_SPCR2_GRST_RESET,                /* GRST   = 0 */
    	MCBSP_SPCR2_XINTM_FRM,                /* XINTM  = 0 */
        0,                                    /* XSYNCERR = N/A */
        MCBSP_SPCR2_XRST_DISABLE              /* XRST   = 0 */
       ),
      MCBSP_RCR1_RMK(
      MCBSP_RCR1_RFRLEN1_OF(31),                /* RFRLEN1 = 0 */
      MCBSP_RCR1_RWDLEN1_32BIT                 /* RWDLEN1 = 5 */
      ),
     MCBSP_RCR2_RMK(
        MCBSP_RCR2_RPHASE_SINGLE,              /* RPHASE  = 0 */
        MCBSP_RCR2_RFRLEN2_OF(0),              /* RFRLEN2 = 0 */
        MCBSP_RCR2_RWDLEN2_16BIT,                /* RWDLEN2 = 0 */
    	MCBSP_RCR2_RCOMPAND_MSB,               /* RCOMPAND = 0 */
        MCBSP_RCR2_RFIG_YES,                   /* RFIG    = 0 */
        MCBSP_RCR2_RDATDLY_1BIT                /* RDATDLY = 0 */
        ),
       MCBSP_XCR1_RMK(
        MCBSP_XCR1_XFRLEN1_OF(31),              /* XFRLEN1 = 0 */
    	MCBSP_XCR1_XWDLEN1_32BIT               /* XWDLEN1 = 0 */
     ),
     MCBSP_XCR2_RMK(
    	MCBSP_XCR2_XPHASE_SINGLE,              /* XPHASE  = 0 */
        MCBSP_XCR2_XFRLEN2_OF(0),              /* XFRLEN2 = 0 */
        MCBSP_XCR2_XWDLEN2_8BIT,               /* XWDLEN2 = 0 */
    	MCBSP_XCR2_XCOMPAND_MSB,               /* XCOMPAND = 0 */
        MCBSP_XCR2_XFIG_YES,                   /* XFIG    = 0 */
        MCBSP_XCR2_XDATDLY_1BIT                /* XDATDLY = 0 */
      ),
     MCBSP_SRGR1_RMK(
       MCBSP_SRGR1_FWID_OF(0),                /* FWID    = 1 */
       MCBSP_SRGR1_CLKGDV_OF(0)               /* CLKGDV  = 1 */
     ),
     MCBSP_SRGR2_RMK(
        MCBSP_SRGR2_GSYNC_FREE,                /* FREE    = 0 */
        MCBSP_SRGR2_CLKSP_RISING,              /* CLKSP   = 0 */
        0,            /* CLKSM   = 1 */
        MCBSP_SRGR2_FSGM_DXR2XSR,              /* FSGM    = 0 */
        MCBSP_SRGR2_FPER_OF(0)                /* FPER    = 0 */
     ),
     0x0001,
     0x0001,
     MCBSP_PCR_RMK(
       MCBSP_PCR_XIOEN_SP,                     /* XIOEN    = 0   */
       MCBSP_PCR_RIOEN_SP,                     /* RIOEN    = 0   */
       MCBSP_PCR_FSXM_EXTERNAL,                /* FSXM     = 1   */
       MCBSP_PCR_FSRM_EXTERNAL,                /* FSRM     = 0   */
       MCBSP_PCR_CLKXM_OUTPUT,                 /* CLKXM    = 1   */
       MCBSP_PCR_CLKRM_INPUT,                  /* CLKRM    = 0   */
       MCBSP_PCR_SCLKME_NO,                    /* SCLKME   = 0   */
       0,                                      /* DXSTAT = N/A   */
       MCBSP_PCR_FSXP_ACTIVEHIGH,              /* FSXP     = 0   */
       MCBSP_PCR_FSRP_ACTIVELOW,              /* FSRP     = 0   */
       MCBSP_PCR_CLKXP_RISING,                 /* CLKXP    = 0   */
       MCBSP_PCR_CLKRP_FALLING                 /* CLKRP    = 0   */
     ),
     MCBSP_RCERA_DEFAULT,
     MCBSP_RCERB_DEFAULT,
     MCBSP_RCERC_DEFAULT,
     MCBSP_RCERD_DEFAULT,
     MCBSP_RCERE_DEFAULT,
     MCBSP_RCERF_DEFAULT,
     MCBSP_RCERG_DEFAULT,
     MCBSP_RCERH_DEFAULT,
     MCBSP_XCERA_DEFAULT,
     MCBSP_XCERB_DEFAULT,
     MCBSP_XCERC_DEFAULT,
     MCBSP_XCERD_DEFAULT,
     MCBSP_XCERE_DEFAULT,
     MCBSP_XCERF_DEFAULT,
     MCBSP_XCERG_DEFAULT,
     MCBSP_XCERH_DEFAULT
    };
    
    
    Int16 MCBSP0_init( )
    {
        McBsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
        MCBSP_config(McBsp0, &ConfigLoopBack32);
        MCBSP_start(McBsp0,MCBSP_XMIT_START,0);
        return 0;
    }
    
    interrupt void McBspTx0Isr(void)
    {
        MCBSP_write32(McBsp0,0x80);
    }
    void Config_McBsp(void)
    {
         IRQ_setVecs((Uint32)(&VECSTART));
         IRQ_globalDisable();
         IRQ_clear(IRQ_EVT_XINT0);
         IRQ_plug(IRQ_EVT_XINT0,&McBspTx0Isr);
         IRQ_enable(IRQ_EVT_XINT0);
         IRQ_globalEnable();
    }
    
    void main(void)
    {
        CSL_init();
        status=1;status1=1;
        PLL_setFreq(        1,        // PLL mode
                            6,       // Multiply factor, Valid values are (multiply by)10
                            0,      // Sysclk 0 Divide Down
                            1,     // Sysclk1 Divider 150MHz
                            1,    // Sysclk2 Divider 75MH+z
                            1,   // Sysclk3 Divider
                            0); // CLKOUT3(DSP core clock) divider 300MHz
        for(i=0;i<CHANNEL;i++)
        {
        	xdata[i]=0;
        	rdata[i]=0;
        }
        MCBSP0_init();
        
        MCBSP_channelEnable(McBsp0,XCERA,0x0001);
        MCBSP_channelEnable(McBsp0,XCERB,0x8000);
        Config_McBsp();
        while(1)
        {
        	
        }
    }

    output :

    Any guidance about this problem??

    Thanks