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AM1705: AM1705 Extended Wait Mode

Michael Andersson
Prodigy 30 points
Part Number: AM1705

Hi,

When using Extended Wait Mode; what are the restrictions on the W_SETUP, W_STROBE and W_HOLD CEnCFG-fields?

When reading the "AM17x/AM18x ARM Microprocessor External Memory Interface A (EMIFA)" (SPRUFV0A) document all I can find regarding restrictions is this:
"If Extended Wait Mode is enabled by setting the EW field in the asynchronous n configuration register (CEnCFG), these fields must be set to a value greater than zero." (see page 27).

However, the ."Technial Reference Manual" (SPRUH93D) specifies the followig:
"... a restriction is placed on the strobe period timing parameters when operating in Extended Wait mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than 4, ..." (see page 742).

Which one is it? If the latter one applies, are there any ways around those pretty slow time specs?

At the moment I'm running with W_SETUP=0, W_STROBE=1, W_HOLD=1 and it seems to work just fine.

Thanks!



  • 0
    TI__Mastermind 29210 points
    Hi Michael,

    I've notified my colleague about this thread.

    See his responses to these related posts:
    e2e.ti.com/.../624148
    e2e.ti.com/.../1420742

    Note that the EMIF16 on these devices is the same as AM1705.

    Regards,
    Mark
  • 0
    TI__Mastermind 42545 points

    Hi Michael,

    The first statement is correct. The second statement I believe is incorrect based on the IP spec for the EMIF. 

    "If Extended Wait Mode is enabled by setting the EW field in the asynchronous n configuration register (CEnCFG), these fields must be set to a value greater than zero."  

    This statement is in the description of read and write strobe. The R_STROBE and W_STROBE defines the strobe width in EMA_CLK cycles, minus one cycle (see Table 31). If this value is set to 0 the strobe width will be one clock cycle but extended wait needs at least two clock cycles to operate correctly. 

    "... a restriction is placed on the strobe period timing parameters when operating in Extended Wait mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than 4, ..." 

    This statement is incorrect. Based on the spec, the minimum number of clock cycles that can be specified for an extended wait access is four, W_SETUP=0 (1 cycle), W_STROBE=1 (2 cycles) and W_HOLD=0 (1 cycle). The extended wait will add additional cycles but they are not specified in the CEnCFG registers. Remember that the extended wait signal is asynchronous and must be present for at least two clock cycles for proper operation. Even if the extended wait signal is held low when the cycle begins a couple of extra clocks will be part of the access. 

    Regards, Bill 

  • 0 in reply to Bill Taboada
    Prodigy 30 points
    Thank you for a quick and informative reply.
    This is very good news to me!
    Regards,
    Michael