How can I use the generic YCbCr interface of VPFE in DM355?

I believe the closest there is to a timing diagram for the VPFE is figure 4 of SPRUF71a, the same document you reference, though this is for the raw mode the same timing scheme is used for the generic YCbCr interface. Essentially the the PCLK will be clocked constantly and the VD will have an edge signifying the start of the frame and the HD will have an edge for the start of each line, either the VPFE or the FPGA can generate the sync signals. The interface can function with just single edges signifying the start of frame and lines because the VPFE will be configured to know the height and width of the incoming image so it knows how many clocks to latch in data for after each sync edge.

Thank you for you help.

I read the SPRUF71a again.I draw the timing scheme,I want to know what I draw is right ro wrong.

My video input is 1280*960,4:2:2 YCbCr format,interlaced.

So the data size is 1280*960*2 bytes.

I want use the 16bit YCbCr interface.The Pclk is 54MHz.

I use PCLK,Y[0..],C[0..7],HD,VD.

                     Figure 1

I will set the MODESET.FLDMODE = 1,because my input video is interlaced.

From the beginning of timer1,I put the Y data to CCDC through Y[0..7] withe the sequence [Y0,Y1,...Y640],and put the CbCr data to CCDC through C[0..7] with the sequence[Cb0,Cr0,Cb1,Cr1,...Cb320,Cr320].

Is there anything wrong?

And I set a HD ,VD signal at the beginning of timer1at the same time .

Should I set the Hd width and pixels per line (HDW, PPLN)  and the Vd width and lines per frame (VDW, HLPFR)?

How long should the HD high level last(the time HDW)?

How long should the VD high level last (the time VDW)?

There are 1280 pixel per line.A pixel is 2 bytes.

There are 960 lines per a picture.

Because the video input is interlaced ,I think  I should set 2 VD signal per picture.

So I draw another picture.

           Figure 2. 

 From the beginning of timer1,I put the even field data,

At first, I put the line1 ,and then I put the line2 ,....line 480.

At the end of line 480 (time3),I put the odd field data.

At the end of line 480 in odd field data (timer 4), I put the even field data of another picture.

Is there anything wrong in it ?

"The interface can function with just single edges signifying the start of frame and lines because the VPFE will be configured to know the height and width of the incoming image so it knows how many clocks to latch in data for after each sync edge."

How can the VPFE know the height and width of the incoming image?

Is there any Register configured for this ?

Would you please help me ?

Thanks!

xrqun@163.com said:

Is there anything wrong?

So far everything seems reasonable however there is typically some 'blanking' space between each line and between each frame so you do not necessarily go directly into the next line after the prior line finishes.

xrqun@163.com said:

How long should the HD high level last(the time HDW)?

How long should the VD high level last (the time VDW)?

This is largely arbitrary in most cases, the signal would have to change states long enough to be reigstered as an edge by the receiver's logic, if the DM355 is the slave (HD/VD as input) than the HD and VD would have to be held high for at least 3nS before and 2nS after a particular PCLK edge to meet their setup and hold requirements by the datasheet, however if you just held them for a few clock cycles that would be perfectly suitable.

xrqun@163.com said:

From the beginning of timer1,I put the even field data,

At first, I put the line1 ,and then I put the line2 ,....line 480.

At the end of line 480 (time3),I put the odd field data.

At the end of line 480 in odd field data (timer 4), I put the even field data of another picture.

Is there anything wrong in it ?

This sounds correct, however there is another signal you will use for interlaced images, the CAM_WEN_FIELD signal, which will indicate an odd or even field, i.e. it will be high or low during each field to show if the field is the even or the odd field.

xrqun@163.com said:

How can the VPFE know the height and width of the incoming image?

Is there any Register configured for this ?

You certainly do configure registers to define the height and width of the incoming image, for the width to be captured you use the NPH register (section 6.1.8) and for the height you define it with the NLV register (section 6.1.11). Both of these registers (and more you will also be using such as offsets) are discussed in SPRUF71a.

Thanks for your help.