Tool/software: Code Composer Studio
Hi,expert,
I want to run DDR test software on J6 EVM. CCS show an error as below:
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU2_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU2_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU2_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU2_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- C66xx_DSP1: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP1: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence DONE! <<<--- C66xx_DSP2: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP2: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence DONE! <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence DONE! <<<--- CortexA15_1: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_1: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence DONE! <<<--- ARP32_EVE_1: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_1: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_2: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_2: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_3: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_3: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_4: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_4: GEL Output: --->>> EVE Memory Map Done! <<<--- IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<--- CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress... CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<---- CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> --- CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<---- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do. DRA7xx_MULTICORE_EnableAllCores() cannot be evaluated. Could not write 0x4AE06510: target is not connected at *((unsigned int *) ((cpu_num==1) ? (((0x4AE00000+0x6000)+0x500)+0x10) : (((0x4AE00000+0x6000)+0x700)+0x210)))=(unsigned int) 0x7 [DRA7xx_multicore_reset.gel:12] at IPUSSClkEnable(1) [DRA7xx_multicore_reset.gel:324] at IPU1SSClkEnable_API() [DRA7xx_multicore_reset.gel:292] at DRA7xx_MULTICORE_EnableAllCores()CortexA15_0: GEL Output: --->>> DRA7xx Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: Core Reset has occurred. CortexA15_0: GEL Output: --->>> DRA7xx PG2.0 GP device <<<--- CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: EVE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: EVE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (1GB total) CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin All Pad Configuration for Vision Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW RGMII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW RGMII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW RGMII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW RGMII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End All Pad Configuration for RGMII usage on EVM Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End All Pad Configuration for Vision Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Target Connect Sequence DONE !!!!! <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.2.0.00004) CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.2.0.00004)
Could you help to check ?
Br, Widic