Other Parts Discussed in Thread: DRA785
a customer using DRA785 would like to understand the jitter for MCAN.
The DPLL_GMAC_DSP clock is used for this.
- Max PLL jitter for the interval of 13 bit times [ns]
- Max PLL jitter for the interval of 10 bit times [ns]
The customer received the TI recommendation to apply following settings for best lock time and jitter behavior:
Multiplier M: 50
Divider N: 0
Fdpll = Fref ×2 ×M / (N + 1) = 20 MHz × 2 × 50 / (0 + 1) = 2000 MHz
Can TI provide jitter information for this setup?