DRA786: DRA785 - MCAN - DPLL_GMAC_DSP jitter

Stefan_Haas

Mastermind 23012 points

Part Number: DRA786
Other Parts Discussed in Thread: DRA785

Hello,

a customer using DRA785 would like to understand the jitter for MCAN.

The DPLL_GMAC_DSP clock is used for this.

Questions:

Max PLL jitter for the interval of 13 bit times [ns]
Max PLL jitter for the interval of 10 bit times [ns]

The customer received the TI recommendation to apply following settings for best lock time and jitter behavior:

Multiplier M: 50

Divider N: 0

Fdpll = Fref ×2 ×M / (N + 1) = 20 MHz × 2 × 50 / (0 + 1) = 2000 MHz

Can TI provide jitter information for this setup?

Thanks, Stefan

over 4 years ago

0 Vivek Dhande over 4 years ago

TI__Expert 5615 points

Hi Stefan,

I do not think we have done jitter measurement for MCAN. Let me check with the team and will get back to you.

Thanks & Regards,
Vivek Dhande.

Texas Instruments (India) Pvt Ltd

0 Stefan_Haas over 4 years ago in reply to Vivek Dhande

TI__Mastermind 23012 points

Thanks, alternatively is there any jitter measurement data for DPLL_GMAC_DSP ?

Stefan

0 Vivek Dhande over 4 years ago in reply to Stefan_Haas

TI__Expert 5615 points

Hi Stefan,

I have asked respective person for this data.

Thanks & Regards,
Vivek Dhande.

Texas Instruments (India) Pvt Ltd

0 kcastille over 4 years ago in reply to Vivek Dhande

TI__Mastermind 46632 points

Our jitter measurements for the interval of 13-bit times showed a STDev of 112.8ps and a Peak to peak of 1.22 ns. TIE ranged from 300ps to 450 ps.

These results are well within tolerance of max phase margin of 10.4 ns AT 5mbps.

Regards,

Kyle

0 Manfred Becker over 4 years ago in reply to kcastille

TI__Expert 4570 points

Kyle,

thanks for passing on results of the jitter measurements. That directly answers question no. 1: "Max PLL jitter for the interval of 13 bit times [ns]". What about the other interval of 10 bit times? Can that be somehow derived from the measurement results for 13 bit times?

Best regards,

Manfred

0 kcastille over 4 years ago in reply to Manfred Becker

TI__Mastermind 46632 points

Manfred,

Is there a particular concern driving the question? We only have data for 13-bit time, but considering 10-bit time is "in the neighborhood" of total time compared to 13-bit time (30% longer) we would expect the jitter during that window to be about the same.

Thanks,

Kyle

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DRA786: DRA785 - MCAN - DPLL_GMAC_DSP jitter