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AM5716: Breakpoint from user application

Hideaki Matsumoto
Genius 9765 points

Part Number: AM5716

Hi,

 

Can address break which is usually used at debugging be used by user application as well ?

 

The customer wants to use it for synchronizing between two of AM5716 to compare between each result. They want to make debug exception occur when Program Counter matched with their set address. After that, the status of two CPUs were checked and task was called.

Is it possible to do that ? They want to use address break, not interrupt.

 

Regards,

Hideaki

 

  • 0
    TI__Guru**** 393215 points

    Hi,

    Breakpoints are part of the debug subsystem, which isn't active when the processor is in normal execution mode. I don't see how this is possible. The debug subsystem is activated at reset release time by the EMU0/1 signal levels. See section 34 in the AM571x TRM for details.

  • 0 in reply to Biser Gatchev-XID
    TI__Genius 9765 points

    Hi Biser,

     

    Thanks for your reply. According to the “Arm Cortex-A15 MPCore Processor Technical Reference Manual Revision: r4p0”, it seems that hardware breakpoints can be used from user application by using some registers such like Breakpoint Control Registers(DBGBCR), Breakpoint Value Registers(DBGBVR), Program Counter Sampling Register(DBGPCSR), etc… via CP14 or 15. Is it possible ?

     

    10.2 Debug register interfaces

    The Debug architecture defines a set of debug registers. The debug register interfaces provide access to these registers from:

    • Software running on the processor, see Processor interfaces.

    • An external debugger, see External debug interface on page 10-35.

     

    10.2.1 Processor interfaces

    The processor has the following interfaces to the debug, performance monitor, and trace registers:

    Debug registers

    This interface is Baseline CP14, Extended CP14, and memory-mapped. You can access the debug register map using the APB slave port. See External debug interface on page 10-35.

    Performance monitor

    This interface is CP15 based and memory-mapped. You can access the performance monitor registers using the APB slave port. See External debug interface on page 10-35.

    Trace registers

    This interface is memory-mapped. See External debug interface on page 10-35.

     

    10.2.2 Breakpoints and watchpoints

    The processor supports six hardware breakpoints, four watchpoints, and a standard Debug Communications Channel (DCC). Four of the breakpoints match only to virtual address and the other two match against either virtual address or context ID, or Virtual Machine Identifier (VMID). All the watchpoints can be linked to two breakpoints to enable a memory request to be trapped in a given process context.

     

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Guru* 93451 points

    Hi Hideaki, this is probably possible as you have shown, but the operations are core centric and are best described in the ARM documentation.  I know you said they don't want to use interrupts, but have they exhausted all possibilities?  It seems that it would be easier to synchronize the processors with interrupts or GPIOs.   They could embed loops or conditional statements in code to trap the processor in an infinite loop and trigger a GPIO, for example.

    Regards,

    James