AM6548: Disabling unused cores in SBL

Marco,

Just so that I understand your use case better, can you confirm that in your setup you are configuring the Dual Cortex R5F in split mode in the SBL and then want to shut down core 1 using SciClient call.  On the EVM the cores come up in lockstep more so please confirm that they are configured in split mode before trying to shut off core 1

I do see in the CSL spec that there are separate LPSC for Core0 and core1 and also there is a AM6 Device ID 245 associated with the AM6_DEC_MCU_CORE1 (245) so this is something that should be possible but you may need to check if there are any clock dependencies and shut them off as well. What is the error code returned by the SYS firmware.

http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am6x/devices.html

Can you please post your full Sciclient call or code used for shutting the core for our analysis. In the meantime, I will check with our design/system team if there is anything that can prevent shutting of the core1. We suspect the power saving from this is not going to be very high given Cortex R cores consume vary low power as compared to A53 cores.  

Marco Ritter said:

Is the source code of the SYS Firmware available?

SYS firmware running on DMSC can be considered to be similar to Boot ROM. It is only provided as a binary image. We are not exposing DMSC  as a programmable subsystem. Also, DMSC firmware in addition to power management and resource management also handle security and firewall in the device so we are not currently distributing the source on ti.com. The SciClient API interface is the only mechanism to communicate with the SYSFW. 

We are working on a utility to parse the hex trace status messages available from the firmware available on the WKUP UART. The trace needs to be enabled using the board_cfg structure 

http://downloads.ti.com/tisci/esd/latest/4_trace/trace.html

Regards,

Rahul 

Hi Rahul,

first of all thank you for your quick reply of my question.

We won`t only shut down core 1 of the R5F cores, we also want to shutdown the unused A53 cores.

At the moment we only tested to shutdown a few unused modules with the SciClient call.

here our small test code:

uint32_t arrayID[19] = {TISCI_DEV_MCU_RTI0, TISCI_DEV_MCU_RTI1, TISCI_DEV_MCU_ADC0,
                          TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG2, TISCI_DEV_GPU0,
                          TISCI_DEV_I2C2, TISCI_DEV_I2C3, TISCI_DEV_MCU_I2C0,
                          TISCI_DEV_WKUP_I2C0, TISCI_DEV_PCIE1, TISCI_DEV_MCSPI1,
                          TISCI_DEV_MCSPI2, TISCI_DEV_MCSPI3, TISCI_DEV_MCSPI4,
                          TISCI_DEV_MCU_MCSPI2, TISCI_DEV_UART2, TISCI_DEV_USB3SS1,
                          TISCI_DEV_SERDES1};



	SBL_log(SBL_LOG_MIN,"\n\n---Start set PM Mode---\n\n\n");
	
	for(i = 0; i < 19; i++)
	{
		statusPM = Sciclient_pmSetModuleState(arrayID[i], TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
		if(statusPM != CSL_PASS)
		{
			SBL_log(SBL_LOG_MIN,"PMsetMode ERROR: %d\n",i);
		}
		else{
			SBL_log(SBL_LOG_MIN,"PMsetMode PASS: %d\n",i);
		}
	}

	SBL_log(SBL_LOG_MIN,"\n\n---End set PM Mode---\n\n\n");
	SBL_log(SBL_LOG_MIN,"---Start get PM Mode---\n\n\n");
	
	
	for(i = 0; i < 19; i++)
	{
		statusPM = Sciclient_pmGetModuleState(arrayID[i], &mode, &res, &cont, SCICLIENT_SERVICE_WAIT_FOREVER);
		if(statusPM != CSL_PASS)
		{
			SBL_log(SBL_LOG_MIN,"PMsetMode ERROR0: %d\n",i);
		}
		else{
			if(mode !=TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF)
			{
				SBL_log(SBL_LOG_MIN,"PMgetMode ERROR1: %d; mode = %d\n",i, mode);
			}
			else
			{
				SBL_log(SBL_LOG_MIN,"PMgetMode PASS: %d; mode = %d\n",i, mode);
			}
		}
	}
	
	SBL_log(SBL_LOG_MIN,"\n\n---End get PM Mode---\n\n\n");

We didn`t get any error messages durring this code, but as I said after readback the ModuleState all Modules are still running.

How can I disable the locked step mode of the R5F cores and change it into split mode?

Best Regards

Marco