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CCS/PROCESSOR-SDK-AM335X: Profibus slave for bare-metal

Part Number: PROCESSOR-SDK-AM335X
Other Parts Discussed in Thread: PROFIBUS, AM3358

Tool/software: Code Composer Studio

Can someone please direct me to sample code showing how to handle profibus transactions?

  • Hi,


    Check this link:
        

    It is located in the AM3358 product folder under Design & Development tab, called PRU-ICSS Industrial Software for Sitara™ Processors

    Best Regards,
    Yordan

  • I need to  direct a GPIO, Hopefully gpio0[1] M18, to the Pru's TX Enable.  We have profibus running but we want to make use of the TX Enable.   I found this snippet...

    g_pL2GlobVar->sel_GPO_GPIO = 0 ; /*PRUSS GPO for TX Enable*/
    g_pL2GlobVar->gpio_address = 0x0; /*Not used as PRUSS GPO is used for TX Enable*/
    g_pL2GlobVar->L3_mem_start_addr = SOC_PRU_ICSS_SHARED_RAM;
    g_pL2GlobVar->pru_base_addr = SOC_PRU_ICSS_DATA_RAM0;
    g_pL2GlobVar->edma_cc_base_addr = SOC_EDMA30CC_0_REGS;

    ...unfortunately TL2GlobVar doesn't have any of these members. 

    Any help please would be appreciated.

    Alex

  • Alex,

    The BSP structures (not Stack) is added in the TL2GlobVar, see L2.h from third_party/protocols/profibus_slave/include:

    // BSP Structures (not Stack)

    unsigned int PruDmaChannel; ///< Pru DMA channel
    byte DmaSetVal[8]; ///< Pattern used in DmaMemSet operation
    u32 saptaboffset[HIGHEST_SAP];///< Lookup table for sap offsets
    unsigned int ArmDmaChannel;///< EDMA channel allocated by host for L7 transfers
    byte PruTxGpioNum;///< Set to n for pr1_pru0_pru_r30[n] used as TX GPIO for PROFIBUS
    byte x7, x8, x9;///< for alignment
    byte tempDmaSetVal[256];///< temp EDMA set value

    /*In case pru_gpo pin is not available for TX GPIO, GPIO pin from the SoC can be used. The following structure
    members can be used for configuring the GPIO pin for TX. Pinmux configuration to use the pin as GPIO and the initialization of the particular GPIO module should be done for this scheme to work properly.
    Maximum throughput of 12Mbaud may not be achievable with this configuration due to the additional latency of the PRU accessing the GPIO */
    byte sel_GPO_GPIO ; ///< TX enable pin is controlled by GPIO or PRU. 1 for PRU and 0 for GPIO
    byte x10, x11, x12;///< for alignment
    u32 gpio_address; ///< GPIO DOUT register address
    u32 L3_mem_start_addr; ///< L3 memory start address
    u32 pru_base_addr; ///< PRU Data memory address for EDMA
    u32 edma_cc_base_addr; ///< EDMA base address

    Regards,
    Garrett

  • Thank you Garrett,

    We need to have the TX Enable come out o M18 gpio0[1].   

    Can you tell me the address 'u32 gpio_address; '  ?

    Also my company would be willing to pay for a working code snippet.   How does that work?

    Alex

  • Alex,

    You may refer to the address assignment for AM572x:

     g_pL2GlobVar->gpio_address =  CSL_MPU_GPIO4_REGS + GPIO_DATAOUT;/*GPIO base address*/

    Where CSL_MPU_GPIO4_REGS  and GPIO_DATAOUT is defined in CSL as:

    #define CSL_MPU_GPIO4_REGS                                                      (0x48059000U)

    :#define CSL_GPIO_DATAOUT                                        (0x13CU)

    Similarly in your case for M18 gpio0[1] in AM335x, you can add the definitions as below:

    #define CSL_MPU_GPIO0_REGS                                                      (0x44E07000U)

    #define CSL_GPIO_DATAOUT                                        (0x13CU)

    in your application as they are not available in the CSL for AM335x.

    The CSL_MPU_GPIO0_REGS based address and CSL_GPIO_DATAOUT address are available from the TRM - 

    You may try to contact Kunbus to see if they can provide your a working code snippet: https://www.kunbus.com/

    Regards,
    Garrett

  • Garrett:   

    I added those members to g_pL2GlobVar and set the values to the new members according to your instructions like so....

    // agreenberg 09122019
    // .... for M18 gpio0[1] in AM335x
    #define CSL_GPIO_DATAOUT (0x13CU)
    #define CSL_MPU_GPIO0_REGS (0x44E07000U)

    g_pL2GlobVar->sel_GPO_GPIO = 0 ; /*PRUSS GPO for TX Enable*/
    g_pL2GlobVar->gpio_address = CSL_MPU_GPIO0_REGS + GPIO_DATAOUT;/*GPIO base address*/
    g_pL2GlobVar->L3_mem_start_addr = SOC_PRU_ICSS_SHARED_RAM;
    g_pL2GlobVar->pru_base_addr = SOC_PRU_ICSS_DATA_RAM0;
    g_pL2GlobVar->edma_cc_base_addr = SOC_EDMA30CC_0_REGS;

    ...BUT what do I do with them??    How are they used?    Where is the API for setting the values?

    *********  Please get me in touch with someone in my time zone.   

    *********   Someone in North America please respond.

  • Alex,

    You can refer to prfi_soc_bsp_init() in AM57xx_bsp.c, and also update as followings

    _pL2GlobVar->PruTxGpioNum =
    1; /*gpio0_1 is used as TX GPIO*/
    g_pL2GlobVar->sel_GPO_GPIO = 1 ; /* GPIO for TX*/

    to "have the TX Enable come out o M18 gpio0[1]". The rest is handled in PRU firmware.

    Kunbus may have North America support as well.

    Regards,

    Garrett