CCS/TDA3LA: Data verification error on new custom tda3xx board

Log of tda3xx custom board
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15x15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: --->>> All Control module lock registers are UNLOCKED <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> Changing RTI1 reaction type to avoid RTI1 resetting the device after 3 minutes... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> Starting IPU A-MMU configurations... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> IPU A-MMU configuration completed. <<<---
Cortex_M4_IPU1_C0: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<---
Cortex_M4_IPU1_C0: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C0: GEL Output: --->>> 15x15 Package Detected(SYSBOOT[7]=0)... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL OPP 0 clock config in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL already locked, now unlocking
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> EVE_VID_DSP DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000C8
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D0
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D8
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x00000130
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 initialization starts (TI 15x15 EVM)... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL clock config for 532MHz is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C0: GEL Output: Launch full leveling
Cortex_M4_IPU1_C0: GEL Output: ERROR: HW-Leveling time-out
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 532MHz Initialization is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Target Connect Sequence DONE !!!!! <<<---
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: For STM based tracing on TI EVMs,
Cortex_M4_IPU1_C0: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Cortex_M4_IPU1_C0: File Loader: Verification failed: Values at address 0x00350000 do not match Please verify target memory and memory map.
Cortex_M4_IPU1_C0: GEL: File: C:\PROCESSOR_SDK\dms\csl_ddr_test_app_ipu1_0_debug.xem4: a data verification error occurred, file load failed.

Hi,

Can you share the map file for this executable?

Address 0x00350000 seems odd, DDR HW leveling also didn't work as per the log.

Is DDR stable on this board after changes?

Are there are other changes you have made in the app?

Regards,

Rishabh

Hi, 

We build the csl_ddr_test_app for tda3xx and we didn't change anything in the app & linker file for tda3xx_ocmc.cmd.  but its is pointing to 0x0030000 instead of 0x4030000

OCMCRAM1_1: org = 0x00300000 len = 0x00040000 /* OCMC RAM1_1*/
OCMCRAM1_2: org = 0x00340000 len = 0x00010000 /* OCMC RAM1_2*/
OCMCRAM1_3: org = 0x00350000 len = 0x00030000 /* OCMC RAM1_3*/

Also I tried to load wspi writer , even I got the load failed 

File Loader: Verification failed: Values at address 0x83500304 do not match Please verify target memory and memory map.

After loading our gel files the ddr memory from 0x80000000 seems to be stable.

What we have to change for gel file related to HW leveling?

Regards

Prakash

I couldn't upload any file in the forum, it seems there is some problems on the forum.

we will check it and let you know the status, before that we can't load any program to the custom board. it shows file loader verification failed.

In our gel log,

we see some timeout error in some of the registers,

CM_L4PER3_DCC1_CLKCTRL, CM_L4PER3_DCC2_CLKCTRL, CM_L4PER3_DCC3_CLKCTRL, CM_L4PER3_DCC4_CLKCTRL these registers values are 0x02030002.

In the clksel bits in clkctrl  shows source as 0x2: Selects SYS_CLK2. 

module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000C8
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D0
Cortex_M4_IPU1_C0: GEL Output: Waiting for module IDLE status....
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D0
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D8
Cortex_M4_IPU1_C0: GEL Output: Waiting for module IDLE status....
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D8
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x00000130
Cortex_M4_IPU1_C0: GEL Output: Waiting for module IDLE status....
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x00000130

Hi,

we don't have sysclk2 on custom board,

We are getting module disabled for the below 

Cortex_M4_IPU1_C0: GEL Output: Module : DCC1 (CD_L4PER3, PD_L4PER)
Cortex_M4_IPU1_C0: GEL Output: Module State : DISABLED
Cortex_M4_IPU1_C0: GEL Output: Clock State : ON
Cortex_M4_IPU1_C0: GEL Output: Power State : ON
Cortex_M4_IPU1_C0: GEL Output: Final State : MODULE DISABLED
Cortex_M4_IPU1_C0: GEL Output: ==========================================
Cortex_M4_IPU1_C0: GEL Output: Module : DCC2 (CD_L4PER3, PD_L4PER)
Cortex_M4_IPU1_C0: GEL Output: Module State : DISABLED
Cortex_M4_IPU1_C0: GEL Output: Clock State : ON
Cortex_M4_IPU1_C0: GEL Output: Power State : ON
Cortex_M4_IPU1_C0: GEL Output: Final State : MODULE DISABLED
Cortex_M4_IPU1_C0: GEL Output: ==========================================
Cortex_M4_IPU1_C0: GEL Output: Module : DCC3 (CD_L4PER3, PD_L4PER)
Cortex_M4_IPU1_C0: GEL Output: Module State : DISABLED
Cortex_M4_IPU1_C0: GEL Output: Clock State : ON
Cortex_M4_IPU1_C0: GEL Output: Power State : ON
Cortex_M4_IPU1_C0: GEL Output: Final State : MODULE DISABLED
Cortex_M4_IPU1_C0: GEL Output: ==========================================
Cortex_M4_IPU1_C0: GEL Output: Module : DCC4 (CD_L4PER3, PD_L4PER)
Cortex_M4_IPU1_C0: GEL Output: Module State : DISABLED
Cortex_M4_IPU1_C0: GEL Output: Clock State : ON
Cortex_M4_IPU1_C0: GEL Output: Power State : ON
Cortex_M4_IPU1_C0: GEL Output: Final State : MODULE DISABLED

Hi,

DDR app is working on EVM, I hope we solved the timeout register error, As per our understanding by default DCC module enabled by sys_clk2, So we changed the register value of DCC1,DCC2,DCC3,DCC4 to 0x01000002, this value selects the sys_clk1. Now we don't get the timeout error.

On custom board we are able to load the sbl-qspi.xem4 on OCMC ram but not csl-ddr app.

Now we have an error on hw-leveling on DDR.

Hi,

We are able to access only half of OCMC ram from 0x0030 0000 to 0x0034FFFF, the size is around 256 KB.

But in Csl ddr test app the linker script is pointing to 0x00350000 , so we get the loading program failed, But EVM we never get the error like this,

OCMCRAM1_1: org = 0x00300000 len = 0x00040000 /* OCMC RAM1_1*/
OCMCRAM1_2: org = 0x00340000 len = 0x00010000 /* OCMC RAM1_2*/
OCMCRAM1_3: org = 0x00350000 len = 0x00030000 /* OCMC RAM1_3*/
/*SBL will use 1 KB of space from address 0x80000000 for EVE */
DDR3_A8: org = 0x80000400 len = (0x02000000 - 0x400) /* 32 MB */
DDR3_DSP: org = 0x82000000 len = 0x02000000 /* 32 MB */
DDR3_M4: org = 0x84000000 len = 0x02000000 /* 32 MB */
DDR3_SR0: org = 0x86000000 len = 0x01000000 /* 16 MB */
DDR3_M3VPSS: org = 0x87000000 len = 0x01000000 /* 16 MB */
}

/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */

SECTIONS
{
.intvecs : load > IRAM_MEM
.intc_text : load > IRAM_MEM
.TI.noinit : load > IRAM_IPU_VTBL

.init : load > OCMCRAM1_3

.text : load > OCMCRAM1_3 /* CODE */
.data : load > OCMCRAM1_3 /* INITIALIZED GLOBAL AND STATIC VARIABLES. */
.bss : load > OCMCRAM1_3 /* UNINITIALIZED OR ZERO INITIALIZED */
/* GLOBAL & STATIC VARIABLES. */
RUN_START(bss_start)
RUN_END(bss_end)
.const : load > OCMCRAM1_3 /* GLOBAL CONSTANTS */
.cinit : load > OCMCRAM1_3
.stack : load > OCMCRAM1_2 /* SOFTWARE SYSTEM STACK */
.plt : load > OCMCRAM1_3
.sysmem : load > OCMCRAM1_3
.my_sect_ddr : load > OCMCRAM1_3

Hi, 

This mapping has done in TDA3xx_cortexM4_common.gel file, 

GEL_MapAddStr(0x40300000, 0, 0x00080000, "R|W|AS4", 0);     /* OCMRAM1 -  */ , the mapping memory has shown in memory map tool in code composer studio.

Regards

Prakash