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TMS320C6742: SDRAM EMIFA configuration via AISgen tool

Part Number: TMS320C6742


We are developing an application in C6742 booting from NOR flash, using the AIS NOR boot, so we are generating the boot image with the AISgen tool. I have some doubts about the registers in the SDRAM tab, the ones related to SDRAM EMIFA. I have been going through the SDRAM configuration procedure for EMIFA as stated in the C6742 Technical Reference Manual and for some fields it is not clear to me the value to be filled. 

The point is that the Manual describes a step-based procedure, consisting in an Auto-Initialization sequence and two procedures, A and B, each of them to be followed in an specific timing scenario. So, I wonder how the bootloader will perform this step by step procedure based on the static values provided by the AISgen tool. I do not really care about the procedure followed as long as it works, but it is not clear to me what is the value I should set for the SR bit in SDCR register. I would clear it and assume the bootloader will perform procedure B, without entering in self-refresh mode, which means this bit will be never set, but I will appreciate a confirmation of that.

Also, in the same register, I assume PD bit must be cleared in the initial configuration, and PDWR bit should be set since it sounds useful to allow refreshing during Power-down mode when. Does it sound reasonable?

Thanks in advance,