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TMS320C6414T: Caclulation of FLOPS (theoretical)

Part Number: TMS320C6414T

Can anyone help me with calculating the (theoretical) FLOPS of a TMS320C6414T?

As far as I know FLPS are caluclated by: "CPU-Cores"x"CPU-sockets"x"cycles per second"x"FLOPS per cycle"

Since the DSPs are fixed point is ther a way to get the equivalent for the FLOPS per cycle? Can the MIPS value, the instructions per cycle or the operations per cycle be used as equvalent (if yes which one)?

Thank you in advance.

  • Hello,

    I'm not aware of a way to convert from FLOPS to MIPS. For the fixed-point C64x, performance benchmarks are typically measured in MIPS or MMACS. These numbers can be found in the device datasheet or technical brief.


  • Hello Sahin,

    thank you for your  answer. The reason I am asking is that DSP or signal processing architectures may be subject to the EAR and fall under the 4A994B (or maybe 4A003), but only if they have an adjusted peak performance of more than 0.0128 weighted TeraFLOPS. So I need to determine the FLOPS to see if our signal processing and image enhancing architecture is not controlled by the CCL and only subject to the EAR with EAR99.

    Maybe anyone has a clue how to get to a conclusion then?

    Thanks in advance.



  • Steffen

    Sahin forwarded this internally - we discussed and I am summarizing the discussion below - this is likely the best we can do to help you....

    The FL in FLOPS stand for floating point. Which means the C64x FLOPS capability is 0 as it cannot do native floating point artihmetic.  Presumably if  one wants to be really theoretical fixed point processor can run SW emulated floating point at something like /100 to /1000 of the MAC number.
    C6414 soft FLOPS performance won’t be close hitting the limit. It won’t even do that many integer operations.
    The MMAC are M (million) integer multiply and accumulate for these cores is in the range of 2400-4400, from that you can deduce that it will not be doing 0.00128T ops of anything much less floating point.

  • Thank you both,

    this is what we also came up with internally. Since we are using multiple cores on one image enhancing architecture we decided to contact BIS to get a final opinion on this issue. If you like I can keep you updated.

    I'm not saying that using FLOPS is a terrible idea for comparing the computational power of architectures, but for some architectures it makes everything very painful.

    With best regards

    Steffen Peilke

  • Thanks Steffen - we will definitely appreciate the final dispositions from you and any inputs/opinion from BIS and your org - if you can post/update - that will be very  much appreciated. 

  • Hello Mukul,

    BIS gave us a similar answer to that what we already concluded. Here is what they wrote to me:

    Hi Steffen,


    The APP formula only applies to processors that are using 64-bit or more floating point operations. If the processors in your architecture do not do floating point, or use less than 64-bit floating point, the APP would be zero.


    Often the manufacturer can provide the APP value for their chip if it applies, so you may be able to get this information from them as well.

    Hope that helps for the future.

    With best regards.