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DRA787: Please check the memory map

Part Number: DRA787
Other Parts Discussed in Thread: SYSBIOS

  • Please check the memory map in attach file, is it workable?

  • Hi,

    which SDK you use?

    Regards,

    Yordan

  • We use ti-processor-sdk-rtos-automotive-dra7xx-evm-04.03.00.05.

    And we don't use vision SDK.

    We use CCS Create projects.

  • Hello,

    Your entire memory map is in the DDR space, so as long as your CPUs have access to that region (MMUs and memory protection units do not prohibit access) you should be okay to place all code and data as indicated. 

    Can you please clarify what you mean by "workable" for your requirements?

    Thanks,
    Stephen

  • Hi Stephen

    Should the memory align, such as 32M align/16M align/8M align?

    When i try to use Large_16M, build failed because not support Large_16M

  • Hi,

    I'm sorry, I don't understand your question.  Can you please clarify:

    • What are you trying to build?
    • Which target CPU are you building for?
    • What do you mean by Large_16M?
    • What is the error you are facing?

    Thanks,
    Stephen

  • Hi Stephen

    We add following config in *.cfg

    /* Enable cache */
    var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
    Cache.enableCache = true;

    var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
    /* map program code/data memory into ammu (cacheable) */
    var entry = AMMU.largePages[0];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_NO;
    entry.logicalAddress = 0x86000000;
    entry.size = AMMU.Large_32M;
    entry.L1_cacheable = AMMU.CachePolicy_CACHEABLE;

    /* map SR_0 ammu (non-cacheable) */
    var entry = AMMU.largePages[1];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_NO;
    entry.logicalAddress = 0x8E000000;
    entry.size = AMMU.Large_32M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;

    /* map ECARX_LOG ammu (non-cacheable) */
    var entry = AMMU.largePages[2];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_NO;
    entry.logicalAddress = 0x87000000;
    /*entry.translatedAddress = 0x87000000; */
    entry.size = AMMU.Large_16M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    /*entry.L1_posted = AMMU.PostedPolicy_NON_POSTED; */
    /*entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; */
    /*entry.L2_posted = AMMU.PostedPolicy_NON_POSTED; */

    When build, there is an error:

    subdir_rules.mk:17: recipe for target 'build-1485544337-inproc' failed

    error: ti.sysbios.hal.ammu.AMMU: "/home/jf/ti/bios_6_52_00_12/packages/ti/sysbios/hal/ammu/AMMU.xs", line 422: ti.sysbios.hal.ammu.AMMU largePages: Large Page Size: Large_16M is not supported on the TDA3XX device.

  • DRA78config.txt
    /*
     * Copyright (c) 2012-2014 Texas Instruments Incorporated - http://www.ti.com
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    /*
     *  ======== config.bld ========
     *
     */
    var Build = xdc.useModule('xdc.bld.BuildEnvironment');
    
    /*  Memory Map
     *
     *  Virtual     Physical        Size            Comment
     *  ------------------------------------------------------------------------
     *  0000_0000   8000_0000       1000  (   4 KB) EVE1_VECS (vector table)
     *              8000_1000    3F_F000  (  ~4 MB) EVE1_PROG (code, data)
     *  0000_0000   8040_0000       1000  (   4 KB) EVE2_VECS (vector table)
     *              8040_1000    3F_F000  (  ~4 MB) EVE2_PROG (code, data)
     *  0000_0000   8080_0000       1000  (   4 KB) EVE3_VECS (vector table)
     *              8080_1000    3F_F000  (  ~4 MB) EVE3_PROG (code, data)
     *  0000_0000   80C0_0000       1000  (   4 KB) EVE4_VECS (vector table)
     *              80C0_1000    3F_F000  (  ~4 MB) EVE4_PROG (code, data)
     *              8100_0000   100_0000  (  16 MB) --------
     *              8200_0000   100_0000  (  16 MB) --------
     *              8300_0000   100_0000  (  16 MB) --------
     *              8400_0000   100_0000  (  16 MB) --------
     *              8500_0000   100_0000  (  16 MB) --------
     *              8600_0000   100_0000  (  16 MB) IPU1 (code, data)       [1]
     *              8600_0000    80_0000  (   8 MB) IPU1-0 (code, data)     [1]
     *              8680_0000    80_0000  (   8 MB) IPI1-1 (code, data)     [1]
     *              8700_0000    20_0000  (   1 MB) Ecarx log share memory
     *              8720_0000   100_0000  (  15 MB) --------
     *              8800_0000   100_0000  (  16 MB) --------
     *              8900_0000   100_0000  (  16 MB) --------
     *              8A00_0000   100_0000  (  16 MB) IPU2 (code, data)       [2]
     *              8B00_0000   100_0000  (  16 MB) HOST (code, data)
     *              8C00_0000   100_0000  (  16 MB) DSP1 (code, data)
     *              8D00_0000   100_0000  (  16 MB) DSP2 (code, data)
     *              8E00_0000   100_0000  (  16 MB) SR_0 (ipc)
     *              8F00_0000   100_0000  (  16 MB) --------
     *
     *  Notes
     *  ------------------------------------------------------------------------
     *  [1] IPU1 implies SMP mode; IPU1-0, IPU1-1 implies non-SMP mode. You
     *  cannot use both at the same time.
     *
     *  [2] IPU2 implies SMP mode.
     */
    
    var SR_0 = {
        name: "SR_0", space: "data", access: "RWX",
        base: 0x8E000000, len: 0x1000000,
        comment: "SR#0 Memory (16 MB)"
    };
    
    var Ecarx_log= {
        name: "Ecarx_log", space: "data", access: "RWX",
        base: 0x87000000, len: 0x200000,
        comment: "Ecarx_log Memory (2 MB)"
    };
    memcount=0;
    var memory = []
    
    memory[memcount++]=["L2_RAM",
                           {
    					      base: 0x20000000,
    						  space: "code/data",
    						  name: "L2_RAM",
    						  len:  0x00010000,
    						  access: "RWX",
    					   }
    				   ];
    memcount++;
    
    memory[memcount++]=["OCMC_RAM",
                           {
    					      base: 0x40300000,
    						  space: "code/data",
    						  name: "OCMC_RAM",
    						  len:  0x00080000,
    						  access: "RWX",
    					   }
    				   ];
    memcount++;
    
    memory[memcount++]=["EXT_RAM",
                           {
    					      base: 0x80000000,
    						  space: "code/data",
    						  name: "EXT_RAM",
    						  len:  0x06000000,
    						  access: "RWX",
    					   }
    				   ];
    memcount++;
    
    memory[memcount++]=["IPU1_0_PROG",
                           {
    					      base: 0x86000000,
    						  space: "code/data",
    						  name: "IPU1_0_PROG",
    						  len:  0x1000000,
    						  access: "RWX",
    					   }
    				   ];
    memcount++;
    
    memory[memcount++]=["SR_0", SR_0 ];
    memcount++;
    
    memory[memcount++]=["Ecarx_log", Ecarx_log ];
    memcount++;
    
    Build.platformTable["ti.platforms.evmTDA3XX:dsp1"] = {
        externalMemoryMap: [
            [ "DSP1_PROG", {
                name: "DSP1_PROG", space: "code/data", access: "RWX",
                base: 0x8C000000, len: 0x1000000,
                comment: "DSP1 Program Memory (16 MB)"
            }],
        /*    [ "DSP1_PROG", {
                name: "DSP1_PROG", space: "code/data", access: "RWX",
                base: 0x83200000, len: 0x1000000,
                comment: "DSP1 Program Memory (16 MB)"
            }],*/
            [ "SR_0", SR_0 ],
            [ "Ecarx_log", Ecarx_log ]
        ],
        codeMemory:  "DSP1_PROG",
        dataMemory:  "DSP1_PROG",
        stackMemory: "DSP1_PROG",
        l1DMode: "32k",
        l1PMode: "32k",
        l2Mode: "128k"
    };
    
    Build.platformTable["ti.platforms.evmTDA3XX:dsp2"] = {
        externalMemoryMap: [
            [ "DSP2_PROG", {
                name: "DSP2_PROG", space: "code/data", access: "RWX",
                base: 0x8D000000, len: 0x1000000,
                comment: "DSP2 Program Memory (16 MB)"
            }],
         /*   [ "DSP2_PROG", {
                name: "DSP2_PROG", space: "code/data", access: "RWX",
                base: 0x86400000, len: 0x1000000,
                comment: "DSP2 Program Memory (16 MB)"
            }],*/
            [ "SR_0", SR_0 ],
            [ "Ecarx_log", Ecarx_log ]
        ],
        codeMemory:  "DSP2_PROG",
        dataMemory:  "DSP2_PROG",
        stackMemory: "DSP2_PROG",
        l1DMode: "32k",
        l1PMode: "32k",
        l2Mode: "128k"
    };
    
    Build.platformTable["ti.platforms.evmTDA3XX:eve1"] = {
        customMemoryMap: memory,
        externalMemoryMap: [
            [ "EVEVECS", { /* name used by SYS/BIOS */
                name: "EVEVECS", space: "code/data", access: "RWX",
                base: 0x80000000, len: 0x1000, page: 0,
                comment: "EVE1 Vector Table (4 KB)"
            }],
            [ "EVE1_PROG", {
                name: "EVE1_PROG", space: "code/data", access: "RWX",
                base: 0x80001000, len: 0x3FF000, page: 1,
                comment: "EVE1 Program Memory (~4 MB)"
            }],
            [ "SR_0", SR_0 ],
            [ "Ecarx_log", Ecarx_log ]
        ],
        codeMemory:  "EVE1_PROG",
    //  dataMemory:  "DMEM",
        dataMemory:  "EVE1_PROG",
    //  stackMemory: "DMEM"
        stackMemory: "EVE1_PROG"
    };
    
    
    
    
    Build.platformTable["ti.platforms.evmTDA3XX:ipu1"] = {
        externalMemoryMap: [
            [ "IPU1_PROG", {
                name: "IPU1_PROG", space: "code/data", access: "RWX",
                base: 0x86000000, len: 0x1000000,
                comment: "IPU1 Program Memory (16 MB)"
            }],
         /*   [ "IPU1_PROG", {
                name: "IPU1_PROG", space: "code/data", access: "RWX",
                base: 0x8C800000, len: 0x1000000,
                comment: "IPU1 Program Memory (16 MB)"
            }],*/
            [ "SR_0", SR_0 ],
            [ "Ecarx_log", Ecarx_log ]
        ],
        codeMemory:  "IPU1_PROG",
        dataMemory:  "IPU1_PROG",
        stackMemory: "IPU1_PROG"
    };
    
    var ipu1_ammu = {
        prog: { /* program memory */
            pa: 0x86000000,
            size: "Large_32M",
            cache: "CachePolicy_CACHEABLE"
        },
        sr0: { /* SR_0 data memory (non-cacheable) */
            pa: 0x8E000000,
            size: "Large_32M",
            cache: "CachePolicy_NON_CACHEABLE"
        },
        ecarx_log: { /* ecarx_log data memory (non-cacheable) */
            pa: 0x87000000,
            size: "Large_32M",
            cache: "CachePolicy_NON_CACHEABLE"
        }
    };
    
    Build.platformTable["ti.platforms.evmTDA3XX:ipu1-0"] = {
        customMemoryMap: memory,
        externalMemoryMap: [
            [ "IPU1_0_PROG", {
                name: "IPU1_0_PROG", space: "code/data", access: "RWX",
                base: 0x86000000, len: 0x800000,
                comment: "IPU1-0 Program Memory (8 MB)"
            }],
            [ "SR_0", SR_0 ],
            [ "Ecarx_log", Ecarx_log ]
        ],
        codeMemory:  "IPU1_0_PROG",
        dataMemory:  "IPU1_0_PROG",
        stackMemory: "IPU1_0_PROG"
    };
    
    var ipu1_0_ammu = {
        prog: { /* program memory */
            pa: 0x86000000,
            size: "Large_32M",
            cache: "CachePolicy_CACHEABLE"
        },
        sr0: { /* SR_0 data memory (non-cacheable) */
            pa: 0x8E000000,
            size: "Large_32M",
            cache: "CachePolicy_NON_CACHEABLE"
        },
        ecarx_log: { /* ecarx_log data memory (non-cacheable) */
            pa: 0x87000000,
            size: "Large_32M",
            cache: "CachePolicy_NON_CACHEABLE"
        }
    };
    
    Build.platformTable["ti.platforms.evmTDA3XX:ipu1-1"] = {
        externalMemoryMap: [
            [ "IPU1_1_PROG", {
                name: "IPU1_1_PROG", space: "code/data", access: "RWX",
                base: 0x86800000, len: 0x800000,
                comment: "IPU1-1 Program Memory (8 MB)"
            }],
            [ "SR_0", SR_0 ],
            [ "Ecarx_log", Ecarx_log ]
        ],
        codeMemory:  "IPU1_1_PROG",
        dataMemory:  "IPU1_1_PROG",
        stackMemory: "IPU1_1_PROG"
    };
    
    /*
     *  ======== ti.targets.elf.C66 ========
     */
    var C66 = xdc.useModule('ti.targets.elf.C66');
    C66.ccOpts.suffix += " -mi10 -mo -pdr -pden -pds=238 -pds=880 -pds1110 ";
    Build.targets.$add(C66);
    

  • The attached file is our memory map, We want to config "Ecarx log share memory" to be noncache. 

    When use Large_16M, there is an build error.

    When use Large_32M, build success, but after boot up, when try to write data to "Ecarx log share memory", the system dead.

  • Hi,

    Thanks for clarifying the issue.

    Please note that on this device, only 32MB and 512MB are the only allowable configurations.  Please refer to section 5.4.4.2 of the TRM for the description for CACHE_MMU_LARGE_POLICY_i[1] SIZE: http://www.ti.com/lit/ug/spruif4d/spruif4d.pdf

    While it is allowed for you to use the different MMU page sizes to create smaller policies within a larger region, you cannot have overlapping regions of the same page size as the transaction is then undefined.  In your configuration, I see large page 0 and large page 2 overlap by 16MB.  Please try aligning "Ecarx log share memory" to the next 32MB boundary at 0x8800_0000, or elsewhere as you see fit, in your memory map.

    Thanks,
    Stephen