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DRA77P: PMIC TPS65917-Q1 VIO_IN timming (document SLVUBC8A)

AClemotte
Expert 1060 points
Part Number: DRA77P

Hi,

According to document SLVUBC8A, "For 3.3-V VIO, a switched version of the 3.3-V supply rail enabled by SMPS5 can be used to supply VIO_IN which allows VIO_IN to be supplied after VCCA, but before GPIO_4 is enabled in the sequence. "

On the other hand, in figure 5 "Power-up sequence" it can be seen that by feeding VIO_IN with SMPS5, the GPIO_2, GPIO_4, INT, RESET_OUT and I2C pins signals will be available, even though the feeding process of the DRA has not been completed. This leads to the scenario where a peripheral (the PMIC) is trying to communicate with the DRA, introducing line tensions, when the DRA is not yet fully powered.

And since "All IO Cells are NOT Fail-safe compliant (DRA) and should not be externally driven in absence of their IO supply" (SPRS993E):


- Is this behaviour dangerous for the DRA?

- Is it not better to feed the VIO_IN with the signal VIO_3V3?

Regards,

  • 0
    TI__Genius 10000 points

    AClemotte,

    Hi, there is no issue with supplying VIO_IN with the 3.3V supply of SMPS5. This means that the digital components of the PMIC will be supplied by when SMPS5 is enabled. It does not meant the digital pins (GPIOs and RESET_OUT) will be enabled at that time. Once supplied, they will continue to be driven low by the PMIC until it is the right time in the power sequence for that digital rail to be enabled.

    Please let me know if this addresses your concerns.

    thanks,

    Nastasha

  • 0 in reply to Nastasha
    Expert 1060 points

    Hi Nastasha,

    Thanks for your comments. Is there any documentation about this?

    Regarding the same document (SLVUBC8A), a note remarks: "The GPIO_0 (...) are open-drain pins and therefore must be pulled up externally. [...]. Therefore, TI recommends pulling this signal up to a sequenced output, such as SMPS5 (1.8 V) or LDO4 (3.3 V).

    As I need a 3V3 signal for GPIO_0, according to TI, my option should be LDO4. But I don't understand how LDO4 can be an option to SMPS5, since the two signals are very temporarily different (SMPS5 is one of the first signals to be enabled, while LDO4 is one of the last). Wouldn't it be better to connect it to VIO_IN_3V3 (SMPS5 at 3V3)?

    Regards,

  • 0 in reply to AClemotte
    TI__Genius 10000 points

    Hi,

    SMPS5 is 1.8V and can be used if you are using a 1.8V level for VIO or the pullup. If you need 3.3V for VIO, see page 4 of that same user guide. It recommends using the 3.3V VCCA for VIO that is sequenced be SMPS5 using an external FET. I agree that LDO4 cannot be used for GPIO_0 since GPIO_0 is enabled first.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Expert 1060 points

    OK, thanks.