Hi TI gurus.
I have a McASP RX ping-pong transfer that runs forever copying RX data to 2 x buffers in L2RAM.
The transfer itself seems fine and never seems to stop working, however I am currently being frustrated by an issue with interrupts.
I find that after some number of transfers (several hundred to several thousand seemingly randomly). The transfer complete interrupt stops actually executing the mapped ISR.
After this occurs I pause code composer and find that the EDMACC0 IPR has both of my TCC bits set.
I next check for events in the INTC0 EVTFLAG register. Sometimes I see event 8 (SYS_INT_EDMA3_0_CC0_INT1) set, and sometimes not.
However I then find that the core IFR is set to 0x0 (I re-checked that it is still mapped to the event).
I am not using an operating system.
What could prevent EDMA IPR bits from generating an INTC event?
What could prevent INTC events from generating a mapped core interrupt?
Is there some sort of race condition possible when clearing down the interrupt?
Many thanks,
James