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TMS320C6652: SPI BOOT MODE

Part Number: TMS320C6652

Hi,

We are using TMS320C6652,

GPIO[13:1] configured for SPI Boot Mode,

As PCIESSMODE[1:0]/GPIO[15:14], and PCIESSEN/TIMI0) are reserved for C6652 ,we have left these pins floating.

We flashed the SP platform application image from DSP (using Volatile Boot) to NOR flash and was able to verify the flash contents.

But when we power cycle the board with boot mode set to NOR SPI boot (boot mode 6) , RBL (Rom Boot Loader) TI firmware in chip supposed to load the image to SRAM and execute it. But this is not working .

Please suggest .

 

Regards,

Spandana.

 

  • Hi,

    Please check http://software-dl.ti.com/processor-sdk-rtos/esd/docs/06_01_00_08/rtos/index_Foundational_Components.html#c66x for NOR boot on C66x. Is this your own C6652 board and do you use IBL?

    Regards, Eric

  • Hi,

    Yes,this is custom board, we are using RBL,SPI Boot and not using the IBL.

    Regards,

    Spandana.

  • Spandana,

    What do you mean by "this is not working"? What is the expected result? E.g.: if your application is LED blink, after boot LED didn't blink?

    Please check:

    1) DEVSTAT register: address at 0x02620020

    Confirm it is indeed doing SPI boot;

    2) Remove GEL file in your CCS configuration, when boot failed, connect CCS, check PC value, is it still  within ROM bootloader? If PC is not in ROM space, that would mean app is already loaded but when application runs, you are not seeing the expected result.

    3) Check your application: your application's memory map shouldn't have conflict with boot ROM, i.e., the memory reserved by ROM bootloader can't be used by your application while loading. After loading, when your application runs, you can use it but just not while loading it.

    4) Are you loading your application into DDR? By default DDR is not initialized. You would need to initialize DDR before you can load into it. Try a simple application without DDR to see that works or not.

    best regards,

    David Zhou

  • Spandana,

    Please also check the direct SPI boot example  here:

    https://processors.wiki.ti.com/index.php/KeystoneI_Bootloader_Resources_and_FAQ#Direct_Boot_Examples_.28without_IBL.29

    specifically this one may be interesting to you:

    C6657 EVM SPI boot example with DDR initialization

    best regards,

    David Zhou

  • Hi,

    Please find the responses for your queries.

    dzhou said:

    Spandana,

    What do you mean by "this is not working"? What is the expected result? E.g.: if your application is LED blink, after boot LED didn't blink?

    Please check:

    1) DEVSTAT register: address at 0x02620020

    Confirm it is indeed doing SPI boot

     the value in B2 is read from DEVSTAT register- . We are using C6652.We verified this value in Evaluation board its same as our custom board.

    We are using the SPI boot as given in below link:

    https://processors.wiki.ti.com/index.php/File:C6657_directROM_Boot_example.zip

    2) Remove GEL file in your CCS configuration, when boot failed, connect CCS, check PC value, is it still  within ROM bootloader? If PC is not in ROM space, that would mean app is already loaded but when application runs, you are not seeing the expected result.

    App is not loaded the RBL is stuck in ROM, please see pic below


    3) Check your application: your application's memory map shouldn't have conflict with boot ROM, i.e., the memory reserved by ROM bootloader can't be used by your application while loading. After loading, when your application runs, you can use it but just not while loading it.

    Attached the app command file "app_cmd.txt"

    App is running good, if we load in to L2Ram using XDS200 debugger.

    Below is the memory map file details:

    ENTRY POINT SYMBOL: "_c_int00"  address: 0080e080

     

     

    MEMORY CONFIGURATION

     

             name            origin    length      used     unused   attr    fill

    ----------------------  --------  ---------  --------  --------  ----  --------

      L2SRAM                00800000   00080000  0000e2cf  00071d31  RW X

      L1DSRAM               00f00000   00003fff  00000000  00003fff  RW X

      MSMCSRAM              0c000000   00200000  00000000  00200000  RW X

     

    4) Are you loading your application into DDR? By default DDR is not initialized. You would need to initialize DDR before you can load into it. Try a simple application without DDR to see that works or not.

    We are NOT using DDR.

    NOR writer application from ti\mcsdk_2_01_02_06\tools\writer\nor\evmc6657l is modified to flash 30K image size from SRAM instead of DDR. Our image size is only 17K (SPI nor rom image size).

     

    Same NOR writer and image is also tested in EVL board and its working fine.

     

    Please see norwriter_success.jpg. image also contains boot image loaded at 0x0890000 (spi boot table). We do power restart to check if app is running from ROM.

    app_cmd.txt
    -c
    -heap  0x41000
    -stack 0xa000
    
    /* Memory Map */
    MEMORY
    {
    
        L1DSRAM (RWX)  : org = 0x0F00000, len = 0x3FFF		
        L2SRAM (RWX)   : org = 0x0800000, len = 0x080000			
        MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000		//only for C6657 we are not using this
    }
    
    SECTIONS
    {
    	.c_int00     > 		L2SRAM
        .csl_vect    >       L2SRAM
        .text        >       L2SRAM
        GROUP (NEAR_DP)
        {
            .neardata
            .rodata
            .bss
        } load       >      L2SRAM
        .stack       >      L2SRAM
        .cinit       >      L2SRAM
        .cio         >      L2SRAM
        .init_array	 >      L2SRAM
        .const       >      L2SRAM
        .data        >      L2SRAM
        .switch      >      L2SRAM
        .sysmem      >      L2SRAM
        .far         >      L2SRAM
        .testMem     >      L2SRAM
        .fardata     >      L2SRAM
        .platform_lib > 	L2SRAM
    }
    

     

    best regards,

    David Zhou

  • Hi,

    The SPI NOR flash which we are using is

    MT25QU128ABA1ESE-0SIT,its different from the one used on Evaluation board.

    Regards,

    Spandana.

  • Spandana,

    Thanks for the info.

    You mentioned you are using 

    https://processors.wiki.ti.com/index.php/File:C6657_directROM_Boot_example.zip

    1) Can you try the application within this SPI boot example, not your application to see if that is good?

    2) Do you have TI EVM to try, not your custom board? Does it work on TI EVM?

    best regards,

    David Zhou

  • hi ,

    1) Can you try the application within this SPI boot example, not your application to see if that is good?

    We shall try and get back.

    2) Do you have TI EVM to try, not your custom board? Does it work on TI EVM?

    We have the TI EVM, our application works on the EVM.

     

    best regards,

    David Zhou

    [/quote]

  • spandana sp said:

    hi ,

    1) Can you try the application within this SPI boot example, not your application to see if that is good?

    Since our application is running on EVM we dint try default application. 

    The program counter is stuck in ROM code address, We tried to debug using the system in target reset and having break point at c_int00, but the program did not reach c_int00. We need your support to debug the RBL.

    2) Do you have TI EVM to try, not your custom board? Does it work on TI EVM?

    We have the TI EVM, our application works on the EVM.

    Our SPI rom image application is running on EVM from NOR. On our custom board we are using the different Flash MT25QU128. Comparing to EVM NOR, our MT25QU128 nor has same commands and functionality. Same driver is working for both flash. NOR writer application is able to access both EVM NOR and Custom board NOR. Only RBL is not working.

    Regards,

    Spandana

  • Spandana,

    When you set up break point, it needs to be a hardware breakpoint, not software breakpoint.

    I still need you to try the basic default application on your custom board. 

    best regards,

    David Zhou

  • Spandana,

    Do you have a complete list of differences between EVM & your custom board? 

    From boot perspective, is DEVSTAT showing the exact value? This means all the pins are sampling the same way?

    best regards,

    David Zhou

  • Hello Spandana,

    What is your status on this issue?

    best regards,

    David Zhou

  • Hi,

    The issue is still open, as suggested by You we tried the basic default binary code ,it did not boot.

    To compare the behavior with EVL board , we need to change the DP switch to “No boot mode” this is not possible, as we are testing remotely, no access to la right now.

    Regards,

    Spandana.

  • Spandana,

    Since none of the working binaries on EVM works on your custom board, so the next step is to check power sequencing and SPI clock to see if this is HW related.

    best reagards,

    David Zhou

  • dzhou said:

    Spandana,

    Do you have a complete list of differences between EVM & your custom board? 

    The major difference is we have not used DDR on our board.

    From boot perspective, is DEVSTAT showing the exact value? This means all the pins are sampling the same way?

    The DEVSTAT showing exact value and the pins are sampling the same way.

    best regards,

    David Zhou

  • Hello,

    I am closing this E2E since the root cause is wrong SPI mode[polarity/phase] setting in boot pins.

    best regards,

    David Zhou