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TMDSEVM6657: TMDSEVM6657LS- multiple SPI transmissions without delay

Part Number: TMDSEVM6657
Other Parts Discussed in Thread: DAC80504EVM, TMS320C6657

Hello everyone,

I am working with TMDSEVM6657LS evaluation board. I would like to use it as master for SPI communication with DAC80504EVM and ADS8920BEVM as slave devices. I have been reading http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf to get more information about the SPI communication that is expected for the TMS320C6657 DSP and I have come to understand that this device is able to send 16 bit transmissions. Since DAC that I would like to use expects continuous streams of 24 bits, and ADC sends 22 bit long transmissions, I was wondering is it possible to send multiple SPI transmissions from this DSP without delay in between, so that it can be read by the DAC?

And also the same for the incomming bits from ADC. From the sprugp2a.pdf I have understood that if in SPIDAT1 REGISTER CSHOLD=1 and CSNR information is maintained the same, while in SPIDAT1 register WDEL=0 (and C2TDELAY=0 and T2CDELAY=0 in SPIDELAY register), I could enable countinuous transmission without any delay in between two transmissions of 16 bit. Is that correct?

I would very much appreciate it if someone could support me with this issue. I will very much appreciate any comment or suggestion.

Thanks in advance,

Kind regards,

Dejana

  • Hi,

    Please see the mentioned doc: 2.5.1.3 Automatic Delay Between Transfers

    The SPI master can automatically insert a delay of between 2 and 65 SPI module clock cycles between transmissions. This delay is controlled by the WDELAY field in the SPI data format register n (SPIFMTn) and is enabled by setting the WDEL bit in the SPI transmit data register (SPIDAT1) to 1. The WDELAY period begins when the T2EDELAY period terminates (if T2E delay period is enabled) or when the T2CDELAY period terminates (if T2E delay period was disabled and T2C delay period was enabled) or when the master deasserts SPISCS[n] (if T2E and T2C delay periods are disabled). If a transfer is initiated by writing a 32-bit value to SPIDAT1, then the new values of SPIDAT1.WDEL and SPIFMTn.WDELAY are used; otherwise, the old values of SPIDAT1.WDEL and SPIFMTn.WDELAY are used. The WDELAY delay period is specified by: Maximum duration of WDELAY period = SPIFMTn.WDELAY + 2 (SPI module clock cycles).

    Regards, Eric

  • Hi Eric,

    Thank you very much for your reply.

    I understand the logics behind the things you already explained. I understood that from the User Guide. Does that however mean that the minimum delay is 2 SPI module clock cycles (WDELAY period = 0 + 2 (SPI module clock cycles)) and that there is no option in which there is no delay at all?

    Then, it is not possible to perform continuous SPI transfer (e.g. more than 16 bits per transfer)?

    Kind regards,

    Dejana

  • Hi,

    Could the delay insertion be disabled by: clear the WDEL bit in the SPI transmit data register?

    Regards, Eric

  • Hi Eric,

    Yes, that was my initial assumption. I just wanted to confirm if my understanding of the SPI guide was alright.

    Thank you very much for your support.

    Kind regards,

    Dejana