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TMS320VC5502: assembly code results in remark R5682 regarding errata CPU_116

Part Number: TMS320VC5502

I am working on change to installed base code which includes source code written in assembly.

The compiler is issuing  remark R5682 regarding errata CPU_118.

I have a few questions:

1) My first question is does this errata apply to my part TMS320VC5502?

It is described in addendum document SPRU652G, Revised February 2005, and is included in the technical documentation for the processor at https://www.ti.com/product/TMS320VC5502/technicaldocuments  as of 4/9/2020

Another document provided is errata document SPRZ020L, Revised June 2007, The document references the above addendum only by document number "SPRU652", without a revision letter.

2) If errata is fixed, which Silicon revision, and how can I identify the revision that we are using?

If errata is not fixed:

3)  Does presence of the remark indicate that the conditions to cause the issue are met (if an interrupt occurs)? If not, I understood the first three conditions described in the errata for the problem to occur, but I don't understand the fourth, "After returning from an interrupt, a specific P-request is stalled with more than two latency cycles".  How can I determine if my code will cause this condition?

3) Can you explain the statement that says that if errata occurs, "the CPU will stop execution". Does this mean the CPU stops entirely, or that the block-repeat loop is exited? (inner or outer)?

Thanks for help.

  • Hi,

    We do not have any collateral or resource beyond what you see in the product folder. You may search the E2E forum for archived posts of previous discussions which may help address your questions. For more info on TMS320VC5502 support, please see the FAQ in 

     https://e2e.ti.com/support/processors/f/791/t/818771

    Rex

  • Alan Owan14 said:

    1) My first question is does this errata apply to my part TMS320VC5502?

    It is described in addendum document SPRU652G, Revised February 2005, and is included in the technical documentation for the processor at https://www.ti.com/product/TMS320VC5502/technicaldocuments  as of 4/9/2020

    Another document provided is errata document SPRZ020L, Revised June 2007, The document references the above addendum only by document number "SPRU652", without a revision letter.

    Yes, Table 1 of SPRU652 indicates that all revisions of the 5502 are impacted.  The 'P' is defined to mean, "The advisory is present on this silicon revision and is related to pipeline protection."

    Alan Owan14 said:

    If errata is not fixed:

    3)  Does presence of the remark indicate that the conditions to cause the issue are met (if an interrupt occurs)? If not, I understood the first three conditions described in the errata for the problem to occur, but I don't understand the fourth, "After returning from an interrupt, a specific P-request is stalled with more than two latency cycles".  How can I determine if my code will cause this condition?

    The remark indicates that the code could be susceptible to the issue.  The first two conditions relate to the code itself.  The last two conditions relate to timing. I'm not 100% sure, but I think "P-request" is a "pipeline request".

    Do you know the maximum number of iterations that loop can iterate in your system?  Another potential workaround that comes to mind is to simply disable interrupts prior to the loop and restore them afterward.  You would need to be very careful about disabling interrupts however.  You don't want to cause excessive interrupt latency that impacts other system functionality.  Another variation might be to disable interrupts prior to the inner loop and restore afterward.

    Alan Owan14 said:
    3) Can you explain the statement that says that if errata occurs, "the CPU will stop execution". Does this mean the CPU stops entirely, or that the block-repeat loop is exited? (inner or outer)?

    Stops entirely.