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66AK2H06: Power-up/down sequencing

Part Number: 66AK2H06

Hi,

I got below questions from my customer for device power-up and power-down sequence.
Customer follows the sequence in datasheet.

Q1) At power-up, as soon as CVDD is on, it seems some voltage leakage is observed on 1.8V and 0.85V power rails.
Is this expected and can be ignored?

Q2) At power-down, there is ~0.5V residual voltage on 1.8V, 1.5V and 0.85V power rails.
Because of this voltage, these rails are higher than CVDD and CVDD1 after CVDD and CVDD1 are off.
Is this also expected and can be ignored?

Please see waveforms attached.
66AK2H06_sequence.xlsx
Thanks and regards,
Koichiro Tashiro

  • Tashiro-san,

    This leakage is known and it will not cause a reliability risk.  The time limits provided as part of the power-up sequence must be met.  Please see the related E2E post linked below.

    There is a leakage path from CVDD to the 1.8V PLL supplies, AVDDA[14:6], the 0.85V SERDES supply, VDDALV, the 1.8V SERDES supply, VDDAHV, and the 0.95V core supply, CVDD1.

    You also ask about power down.  The requirement is that the supplies ramp down in the reverse order of the ramp up.  If that cannot be met, then they all must be turned off simultaneously so that they ramp down together.

    Tom

    https://e2e.ti.com/support/processors/f/791/t/388652?66AK2H-leakage-onto-other-power-rail

  • Hi Tom,

    I understood the answer to Q1, but it is not clear what is answer to Q2.

    Customer did power down in the reverse order of the ramp up, but the residual voltage causes the condition some rails are higher than CVDD and CVDD1.
    Do you mean the waveform customer observed in power-down sequence is *not* valid?

    Thanks and regards,
    Koichiro Tashiro

  • Tashiro-san,

    > Q2) At power-down, there is ~0.5V residual voltage on 1.8V, 1.5V and 0.85V power rails.
    > Because of this voltage, these rails are higher than CVDD and CVDD1 after CVDD and CVDD1 are off.
    > Is this also expected and can be ignored?

    My answer to that question is valid but I guess it is lacking in specifics.  The supplies should ramp down in reversed sequence or essentially simultaneously.  None can remain powered after the others are powered down.  Otherwise this could impact device reliability.  0.5V is not really OFF.  We prefer that the supplies are below 0.3V when they are OFF although this is not a characterized value.

    Where is the source for the residual 0.5V on the 1.8V, 1.5V and 0.85V rails?  I originally assumed it was residual from the CVDD supply that was previously present.  Now, after more consideration, I am guessing it is from another source.  This may be a concern.

    Tom

  • Tashiro-san,

    Can this be closed or is there other information needed?

    Tom

  • Hi Tom,

    Sorry for the late reply.
    Customer did some investigation and concluded below points.

    a) The residual voltage on 1.8V, 0.85V are clearly coming from CVDD.
    As soon as CVDD is off, 1.8V and 0.85V also start decreasing.
    As 1.8V has much bigger load capacity, 1.8V is decreasing much slower.


    b) The residual voltage on 1.5V and 3.3V are simply because these power rails has bigger capacitance.
    1.5V is used for DDR and has a lot of decoupling capacitors.
    3.3V is used anywhere on the board.
    It takes long time(~ a several seconds) these voltage go under 0.3V.


    Customer is afraid there is no realistic way to meet the power down requirement, i.e. the residual voltage needs to be below 0.3V.
    How other customers manage this?

    Thanks and regards,
    Koichiro Tashiro

  • Tashiro-san,

    This is not a problem.  The supplies have been sequenced off in an acceptable order.  The supplies are decaying are only held up by the decoupling once the CVDD is off.  My remaining concern above was that their was leakage on youe board from another supply that was still powered.  Since that is not happening, this implementation meets the requirements.

    Tom