Hello :
we are working on our custom board with visonsdk 3.05.
recentlly we change the PMIC solution from O917A154+87565 to O917A133,
here is the hardware schema
and the log
2313.pmic.log
[22:42:04:519] [22:42:04:520]U-Boot SPL 2016.05 (Apr 22 2020 - 02:33:09) [22:42:04:523]DRA752-GP ES2.0 [22:42:04:575]no pinctrl for hs200_1_8v [22:42:04:576]no pinctrl for ddr_1_8v [22:42:04:820]** First descriptor is NOT a primary desc on 1:1 ** [22:42:04:821]*** Warning - bad CRC, using default environment [22:42:04:821] [22:42:04:842]Trying to boot from MMC1 [22:42:04:842]reading dra7-ipu2-fw.lzop [22:42:04:843]spl_load_file_fat: error reading file dra7-ipu2-fw.lzop, err - -1 [22:42:04:858]spl: error reading image dra7-ipu2-fw.lzop, err - -1 [22:42:04:858]Error loading remotecore IPU2!,Continuing with boot ... [22:42:04:859]reading dra7-dsp1-fw.lzop [22:42:04:872]spl_load_file_fat: error reading file dra7-dsp1-fw.lzop, err - -1 [22:42:04:873]spl: error reading image dra7-dsp1-fw.lzop, err - -1 [22:42:04:885]Error loading remotecore DSP1!,Continuing with boot ... [22:42:04:886]reading dra7-dsp2-fw.lzop [22:42:04:886]spl_load_file_fat: error reading file dra7-dsp2-fw.lzop, err - -1 [22:42:04:886]spl: error reading image dra7-dsp2-fw.lzop, err - -1 [22:42:04:887]Error loading remotecore DSP2!,Continuing with boot ... [22:42:04:901]reading dra7-ipu1-fw.lzop [22:42:04:901]spl_load_file_fat: error reading file dra7-ipu1-fw.lzop, err - -1 [22:42:04:903]spl: error reading image dra7-ipu1-fw.lzop, err - -1 [22:42:04:918]Error loading remotecore IPU1!,Continuing with boot ... [22:42:04:918]*** Warning - bad CRC, using default environment [22:42:04:918] [22:42:04:919]reading u-boot.img [22:42:04:931]reading u-boot.img [22:42:04:932]reading u-boot.img [22:42:04:950]reading u-boot.img [22:42:05:266] [22:42:05:266] [22:42:05:267]U-Boot 2016.05 (Apr 22 2020 - 02:33:09 +0000), Build: jenkins-kunpeng_build_package-187 [22:42:05:267] [22:42:05:267]CPU : DRA752-GP ES2.0 [22:42:05:278]Model: TI DRA742 [22:42:05:278]Board: DRA74x EVM REV [22:42:05:280]DRAM: 1 GiB [22:42:05:396]MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 [22:42:05:526]** First descriptor is NOT a primary desc on 1:1 ** [22:42:05:527]*** Warning - bad CRC, using default environment [22:42:05:527] [22:42:05:541]Warning: fastboot.board_rev: unknown board revision [22:42:05:542]GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645 [22:42:05:551]part_get_info_efi: *** ERROR: Invalid GPT *** [22:42:05:552]GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645 [22:42:05:563]part_get_info_efi: *** ERROR: Invalid Backup GPT *** [22:42:05:563]ERROR: cannot find partition: 'userdata' [22:42:05:564] [22:42:05:576]at arch/arm/cpu/armv7/omap-common/utils.c:199/mmc_get_part_size() [22:42:05:576]Warning: fastboot.userdata_size: unable to calc [22:42:05:776]SCSI: SATA link 0 timeout. [22:42:05:777]AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode [22:42:05:788]flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst [22:42:05:789]scanning bus for devices... [22:42:05:792]Found 0 device(s). [22:42:05:800]Net: Could not get PHY for ethernet@48484000: addr 1 [22:42:05:800] [22:42:05:801]Warning: ethernet@48484000 using MAC address from ROM [22:42:05:811]eth0: ethernet@48484000 [22:42:07:819]Hit any key to stop autoboot: 0 [22:42:07:820]## Error: "board_findfdt" not defined [22:42:07:963]switch to partitions #0, OK [22:42:07:964]mmc0 is current device [22:42:08:062]SD/MMC found on device 0 [22:42:08:063]reading boot.scr [22:42:08:063]** Unable to read file boot.scr ** [22:42:08:067]reading uEnv.txt [22:42:08:077]175 bytes read in 2 ms (85 KiB/s) [22:42:08:078]Loaded env from uEnv.txt [22:42:08:079]Importing environment from mmc0 ... [22:42:08:167]switch to partitions #0, OK [22:42:08:169]mmc0 is current device [22:42:08:257]SD/MMC found on device 0 [22:42:08:429]3566696 bytes read in 166 ms (20.5 MiB/s) [22:42:08:470]106366 bytes read in 34 ms (3 MiB/s) [22:42:08:471]Booting from mmc0 ... [22:42:08:472]Kernel image @ 0x82000000 [ 0x000000 - 0x366c68 ] [22:42:08:487]## Flattened Device Tree blob at 88000000 [22:42:08:492] Booting using the fdt blob at 0x88000000 [22:42:08:502] Loading Device Tree to 8ffe3000, end 8fffff7d ... OK [22:42:08:502] [22:42:08:503]Starting kernel ... [22:42:08:506] [22:42:11:961][ 0.000000] Booting Linux on physical CPU 0x0 [22:42:11:962][ 0.000000] Initializing cgroup subsys cpuset [22:42:11:979][ 0.000000] Initializing cgroup subsys cpu [22:42:11:980][ 0.000000] Initializing cgroup subsys cpuacct [22:42:11:990][ 0.000000] Linux version 4.4.84 (root@kunpeng-compilesalve-new-6c56z) (gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02) ) #1 SMP PREEMPT Wed Apr 22 02:36:58 UTC 2020 [22:42:12:004][ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d [22:42:12:015][ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache [22:42:12:016][ 0.000000] Machine model: TI DRA742 [22:42:12:030][ 0.000000] Reserved memory: created DMA memory pool at 0x40300000, size 3 MiB [22:42:12:031][ 0.000000] Reserved memory: initialized node cmem@40300000, compatible id shared-dma-pool [22:42:12:032][ 0.000000] Reserved memory: regions without no-map are not yet supported [22:42:12:039][ 0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 80 MiB [22:42:12:043][ 0.000000] Reserved memory: initialized node ipu2_cma@99000000, compatible id shared-dma-pool [22:42:12:054][ 0.000000] Reserved memory: created CMA memory pool at 0x9e000000, size 32 MiB [22:42:12:064][ 0.000000] Reserved memory: initialized node ipu1_cma@9E000000, compatible id shared-dma-pool [22:42:12:067][ 0.000000] Reserved memory: regions without no-map are not yet supported [22:42:12:073][ 0.000000] Reserved memory: created CMA memory pool at 0xa1000000, size 32 MiB [22:42:12:085][ 0.000000] Reserved memory: initialized node dsp1_cma@A1000000, compatible id shared-dma-pool [22:42:12:102][ 0.000000] Reserved memory: created CMA memory pool at 0xa3000000, size 32 MiB [22:42:12:103][ 0.000000] Reserved memory: initialized node dsp2_cma@A3000000, compatible id shared-dma-pool [22:42:12:108][ 0.000000] Reserved memory: regions without no-map are not yet supported [22:42:12:120][ 0.000000] Reserved memory: created DMA memory pool at 0xa9000000, size 32 MiB [22:42:12:120][ 0.000000] Reserved memory: initialized node cmem@A9000000, compatible id shared-dma-pool [22:42:12:134][ 0.000000] cma: Reserved 128 MiB at 0xb7c00000 [22:42:12:135][ 0.000000] Memory policy: Data cache writealloc [22:42:12:142][ 0.000000] OMAP4: Map 0xbfe00000 to fe600000 for dram barrier [22:42:12:147][ 0.000000] DRA752 ES2.0 [22:42:12:158][ 0.000000] PERCPU: Embedded 11 pages/cpu @ef631000 s14912 r8192 d21952 u45056 [22:42:12:159][ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 251712 [22:42:12:168][ 0.000000] Kernel command line: console=ttyS0,115200n8 vram=16M root=PARTUUID=bbb167d9-02 rw rootwait ip=none mem=1024M cma=128M [22:42:12:178][ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [22:42:12:180][ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [22:42:12:186][ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [22:42:12:195][ 0.000000] Memory: 386972K/1013760K available (6679K kernel code, 319K rwdata, 2396K rodata, 336K init, 286K bss, 315492K reserved, 311296K cma-reserved, 129024K highmem) [22:42:12:213][ 0.000000] Virtual kernel memory layout: [22:42:12:214][ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [22:42:12:222][ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB) [22:42:12:225][ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB) [22:42:12:234][ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB) [22:42:12:235][ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [22:42:12:249][ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [22:42:12:250][ 0.000000] .text : 0xc0008000 - 0xc08e500c (9077 kB) [22:42:12:259][ 0.000000] .init : 0xc08e6000 - 0xc093a000 ( 336 kB) [22:42:12:261][ 0.000000] .data : 0xc093a000 - 0xc0989e60 ( 320 kB) [22:42:12:266][ 0.000000] .bss : 0xc098b000 - 0xc09d2980 ( 287 kB) [22:42:12:278][ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [22:42:12:279][ 0.000000] Preemptible hierarchical RCU implementation. [22:42:12:291][ 0.000000] Build-time adjustment of leaf fanout to 32. [22:42:12:292][ 0.000000] NR_IRQS:16 nr_irqs:16 16 [22:42:12:300][ 0.000000] ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div [22:42:12:301][ 0.000000] OMAP clockevent source: timer1 at 32786 Hz [22:42:12:310][ 0.000000] Architected cp15 timer(s) running at 6.14MHz (phys). [22:42:12:321][ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns [22:42:12:322][ 0.000004] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns [22:42:12:328][ 0.000016] Switching to timer-based delay loop, resolution 162ns [22:42:12:342][ 0.000334] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns [22:42:12:343][ 0.000342] OMAP clocksource: 32k_counter at 32768 Hz [22:42:12:355][ 0.000794] Console: colour dummy device 80x30 [22:42:12:356][ 0.000818] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475) [22:42:12:369][ 0.000831] pid_max: default: 32768 minimum: 301 [22:42:12:369][ 0.000928] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [22:42:12:380][ 0.000939] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [22:42:12:382][ 0.001511] Initializing cgroup subsys io [22:42:12:389][ 0.001527] Initializing cgroup subsys memory [22:42:12:390][ 0.001553] Initializing cgroup subsys devices [22:42:12:402][ 0.001565] Initializing cgroup subsys freezer [22:42:12:402][ 0.001577] Initializing cgroup subsys perf_event [22:42:12:403][ 0.001587] Initializing cgroup subsys pids [22:42:12:412][ 0.001613] CPU: Testing write buffer coherency: ok [22:42:12:413][ 0.001836] /cpus/cpu@0 missing clock-frequency property [22:42:12:424][ 0.001851] /cpus/cpu@1 missing clock-frequency property [22:42:12:428][ 0.001862] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [22:42:12:436][ 0.001902] Setting up static identity map for 0x80008340 - 0x800083a0 [22:42:12:437][ 0.080108] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [22:42:12:449][ 0.080176] Brought up 2 CPUs [22:42:12:450][ 0.080189] SMP: Total of 2 processors activated (24.59 BogoMIPS). [22:42:12:465][ 0.080196] CPU: All CPU(s) started in HYP mode. [22:42:12:466][ 0.080202] CPU: Virtualization extensions available. [22:42:12:466][ 0.081242] devtmpfs: initialized [22:42:12:467][ 0.110027] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0 [22:42:12:480][ 0.110986] omap_hwmod: l3_main_2 using broken dt data from ocp [22:42:12:481][ 0.314320] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [22:42:12:486][ 0.314342] futex hash table entries: 512 (order: 3, 32768 bytes) [22:42:12:498][ 0.320884] pinctrl core: initialized pinctrl subsystem [22:42:12:499][ 0.321770] NET: Registered protocol family 16 [22:42:12:511][ 0.322763] DMA: preallocated 256 KiB pool for atomic coherent allocations [22:42:12:511][ 0.360243] cpuidle: using governor ladder [22:42:12:512][ 0.390271] cpuidle: using governor menu [22:42:12:527][ 0.398984] OMAP GPIO hardware version 0.1 [22:42:12:528][ 0.405571] irq: no irq domain found for /ocp/l4@4a000000/scm@2000/pinmux@1400 ! [22:42:12:536][ 0.422210] omap-gpmc 50000000.gpmc: GPMC revision 6.0 [22:42:12:538][ 0.422222] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000 [22:42:12:544][ 0.431305] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers. [22:42:12:557][ 0.431315] hw-breakpoint: maximum watchpoint size is 8 bytes. [22:42:12:559][ 0.431804] omap4_sram_init:Unable to allocate sram needed to handle errata I688 [22:42:12:572][ 0.431813] omap4_sram_init:Unable to get sram pool needed to handle errata I688 [22:42:12:573][ 0.432305] OMAP DMA hardware revision 0.0 [22:42:12:586][ 0.471704] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported) [22:42:12:587][ 0.472877] edma 43300000.edma: memcpy is disabled [22:42:12:596][ 0.477616] edma 43300000.edma: TI EDMA DMA engine driver [22:42:12:600][ 0.482650] omap-iommu 40d01000.mmu: 40d01000.mmu registered [22:42:12:607][ 0.482842] omap-iommu 40d02000.mmu: 40d02000.mmu registered [22:42:12:619][ 0.483000] omap-iommu 58882000.mmu: 58882000.mmu registered [22:42:12:621][ 0.483165] omap-iommu 55082000.mmu: 55082000.mmu registered [22:42:12:636][ 0.483444] omap-iommu 41501000.mmu: 41501000.mmu registered [22:42:12:636][ 0.483629] omap-iommu 41502000.mmu: 41502000.mmu registered [22:42:12:637][ 0.486670] palmas 0-0058: IRQ missing: skipping irq request [22:42:12:638][ 1.523576] palmas: probe of 0-0058 failed with error -121 [22:42:12:651][ 1.523839] pcf857x: probe of 0-0020 failed with error -121 [22:42:12:652][ 1.524085] pcf857x: probe of 0-0021 failed with error -121 [22:42:12:669][ 1.524240] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz [22:42:12:669][ 1.524640] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz [22:42:12:671][ 1.524840] media: Linux media interface: v0.10 [22:42:12:686][ 1.524891] Linux video capture interface: v2.00 [22:42:12:686][ 1.524931] pps_core: LinuxPPS API ver. 1 registered [22:42:12:687][ 1.524939] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [22:42:12:691][ 1.524963] PTP clock support registered [22:42:12:702][ 1.525012] EDAC MC: Ver: 3.0.0 [22:42:12:703][ 1.525762] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400 [22:42:12:703][ 1.526056] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400 [22:42:12:708][ 1.526385] Advanced Linux Sound Architecture Driver Initialized. [22:42:12:718][ 1.527235] clocksource: Switched to clocksource arch_sys_counter [22:42:12:719][ 1.537662] NET: Registered protocol family 2 [22:42:12:734][ 1.538159] TCP established hash table entries: 8192 (order: 3, 32768 bytes) [22:42:12:734][ 1.538223] TCP bind hash table entries: 8192 (order: 4, 65536 bytes) [22:42:12:737][ 1.538348] TCP: Hash tables configured (established 8192 bind 8192) [22:42:12:748][ 1.538400] UDP hash table entries: 512 (order: 2, 16384 bytes) [22:42:12:751][ 1.538431] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [22:42:12:764][ 1.538637] NET: Registered protocol family 1 [22:42:12:765][ 1.538898] RPC: Registered named UNIX socket transport module. [22:42:12:779][ 1.538906] RPC: Registered udp transport module. [22:42:12:779][ 1.538913] RPC: Registered tcp transport module. [22:42:12:779][ 1.538919] RPC: Registered tcp NFSv4.1 backchannel transport module. [22:42:12:781][ 1.539943] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available [22:42:12:789][ 1.548955] squashfs: version 4.0 (2009/01/31) Phillip Lougher [22:42:12:793][ 1.549591] NFS: Registering the id_resolver key type [22:42:12:807][ 1.549620] Key type id_resolver registered [22:42:12:807][ 1.549628] Key type id_legacy registered [22:42:12:809][ 1.549684] ntfs: driver 2.1.32 [Flags: R/O]. [22:42:12:823][ 1.550942] bounce: pool size: 64 pages [22:42:12:824][ 1.551088] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247) [22:42:12:824][ 1.551103] io scheduler noop registered [22:42:12:825][ 1.551115] io scheduler deadline registered [22:42:12:839][ 1.551147] io scheduler cfq registered (default) [22:42:12:840][ 1.555587] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128 [22:42:12:856][ 1.558817] PCI host bridge /ocp/axi@0/pcie_rc@51000000 ranges: [22:42:12:857][ 1.558830] No bus range found for /ocp/axi@0/pcie_rc@51000000, using [bus 00-ff] [22:42:12:857][ 1.558864] IO 0x20003000..0x20012fff -> 0x00000000 [22:42:12:860][ 1.558885] MEM 0x20013000..0x2fffffff -> 0x20013000 [22:42:12:875][ 1.588856] dra7-pcie 51000000.pcie_rc: link is not up [22:42:12:878][ 1.589031] dra7-pcie 51000000.pcie_rc: PCI host bridge to bus 0000:00 [22:42:12:890][ 1.589045] pci_bus 0000:00: root bus resource [bus 00-ff] [22:42:12:890][ 1.589055] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [22:42:12:891][ 1.589065] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff] [22:42:12:908][ 1.589467] PCI: bus0: Fast back to back transfers disabled [22:42:12:909][ 1.589592] PCI: bus1: Fast back to back transfers enabled [22:42:12:923][ 1.589675] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff] [22:42:12:924][ 1.589689] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff] [22:42:12:939][ 1.589702] pci 0000:00:00.0: PCI bridge to [bus 01] [22:42:12:940][ 1.589925] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt [22:42:12:940][ 1.649859] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled [22:42:12:944][ 1.653231] console [ttyS0] disabled [22:42:12:955][ 1.653284] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 301, base_baud = 3000000) is a 8250 [22:42:12:958][ 2.643751] console [ttyS0] enabled [22:42:12:966][ 2.648169] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 302, base_baud = 3000000) is a 8250 [22:42:12:978][ 2.657840] 4ae2b000.serial: ttyS9 at MMIO 0x4ae2b000 (irq = 303, base_baud = 3000000) is a 8250 [22:42:12:979][ 2.667891] [drm] Initialized drm 1.1.0 20060810 [22:42:12:996][ 2.673400] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [22:42:12:996][ 2.680086] [drm] No driver support for vblank timestamp query. [22:42:12:997][ 2.686215] [drm] Initialized vdrm 1.0.0 20110917 on minor 0 [22:42:13:012][ 2.699304] loop: module loaded [22:42:13:012][ 2.702800] vmemexp device MAJOR num = 245 [22:42:13:013][ 2.706925] vmemexp class registered [22:42:13:028][ 2.710653] /dev/vmemexp device registered [22:42:13:029][ 2.714765] ioctl DBUFIOC_EXPORT_VIRTMEM = -1072899120 [22:42:13:043][ 2.720461] nand: No NAND device found [22:42:13:045][ 2.724230] omap2-nand 8000000.nand: scan failed, may be bus-width mismatch [22:42:13:055][ 2.734012] m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 0, 0 [22:42:13:059][ 2.741755] libphy: Fixed MDIO Bus: probed [22:42:13:106][ 2.797266] davinci_mdio 48485000.mdio: davinci mdio revision 1.6 [22:42:13:107][ 2.803390] libphy: 48485000.mdio: probed [22:42:13:118][ 2.808098] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver Marvell 88E1510 [22:42:13:132][ 2.816837] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver RTL9000A Gigabit Ethernet [22:42:13:142][ 2.827095] cpsw 48484000.ethernet: Detected MACID = 4c:3f:d3:15:a2:74 [22:42:13:146][ 2.833765] cpsw 48484000.ethernet: cpts: overflow check period 800 [22:42:13:155][ 2.840738] cpsw 48484000.ethernet: cpsw: Detected MACID = 4c:3f:d3:15:a2:75 [22:42:13:156][ 2.848372] PPP generic driver version 2.4.2 [22:42:13:169][ 2.853829] mousedev: PS/2 mouse device common for all mice [22:42:13:170][ 2.860021] i2c /dev entries driver [22:42:13:183][ 2.868772] omap_hsmmc 4809c000.mmc: Got CD GPIO [22:42:13:184][ 2.874528] omap_hsmmc 480b4000.mmc: no pinctrl state for sdr25 mode [22:42:13:199][ 2.880930] omap_hsmmc 480b4000.mmc: no pinctrl state for sdr12 mode [22:42:13:199][ 2.887517] vsys_3v3: supplied by vsys_12v0 [22:42:13:200][ 2.891756] evm_3v3_sw: supplied by vsys_3v3 [22:42:13:249][ 2.931255] ledtrig-cpu: registered to indicate activity on CPUs [22:42:13:250][ 2.940123] aic_dvdd: supplied by evm_3v3_sw [22:42:13:263][ 2.948505] davinci-mcasp 4847c000.mcasp: invalid tdm slots: 0 [22:42:13:264][ 2.955929] NET: Registered protocol family 10 [22:42:13:280][ 2.971257] sit: IPv6 over IPv4 tunneling driver [22:42:13:281][ 2.976438] NET: Registered protocol family 17 [22:42:13:296][ 2.980587] mmc0: MAN_BKOPS_EN bit is not set [22:42:13:298][ 2.985528] Key type dns_resolver registered [22:42:13:312][ 2.988731] mmc0: new HS200 MMC card at address 0001 [22:42:13:318][ 2.994966] omap_voltage_late_init: Voltage driver support not added [22:42:13:328][ 2.999223] mmcblk0: mmc0:0001 DG4008 7.28 GiB [22:42:13:329][ 3.006413] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm [22:42:13:329][ 3.009514] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB [22:42:13:333][ 3.018615] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm [22:42:13:342][ 3.019779] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB [22:42:13:343][ 3.030862] ti_oppdm 4a003b20.oppdm: Unable to get vdd regulator:-517 [22:42:13:356][ 3.037529] Power Management for TI OMAP4+ devices. [22:42:13:357][ 3.042633] Registering SWP/SWPB emulation handler [22:42:13:372][ 3.048820] dmm 4e000000.dmm: workaround for errata i878 in use [22:42:13:372][ 3.056285] dmm 4e000000.dmm: initialized all PAT entries [22:42:13:374][ 3.062744] [drm] Initialized omapdrm 1.0.0 20110917 on minor 1 [22:42:13:388][ 3.080167] omap_hsmmc 4809c000.mmc: Got CD GPIO [22:42:13:401][ 3.087185] asoc-simple-card sound0: tlv320aic3x-hifi <-> 48468000.mcasp mapping ok [22:42:13:414][ 3.106873] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm [22:42:13:428][ 3.113107] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm [22:42:13:431][ 3.119368] ti_oppdm 4a003b20.oppdm: Unable to get vdd regulator:-517 [22:42:13:442][ 3.127147] omap_hsmmc 4809c000.mmc: Got CD GPIO [22:42:13:445][ 3.133128] hctosys: unable to open rtc device (rtc0) [22:42:13:465][ 3.150162] aic_dvdd: disabling [22:42:13:465][ 3.153329] pbias_mmc_omap5: disabling [22:42:13:466][ 3.157340] ALSA device list: [22:42:13:479][ 3.160320] #0: DRA7xx-EVM [22:42:13:480][ 3.164101] Waiting for root device PARTUUID=bbb167d9-02...
and the dts:
3660.dra7-evm.txt
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra74x.dtsi"
#include "dra7-evm-common.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "TI DRA742";
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
reserved_mem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ipu2_cma_pool: ipu2_cma@99000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x99000000 0x0 0x5000000>;
reusable;
status = "okay";
};
dsp1_cma_pool: dsp1_cma@A1000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xA1000000 0x0 0x2000000>;
reusable;
status = "okay";
};
ipu1_cma_pool: ipu1_cma@9E000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9E000000 0x0 0x2000000>;
reusable;
status = "okay";
};
dsp2_cma_pool: dsp2_cma@A3000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xA3000000 0x0 0x2000000>;
reusable;
status = "okay";
};
};
aliases {
i2c7 = &disp_ser;
};
vsys_12v0: fixedregulator-vsys12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "vsys_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vsys_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_12v0>;
regulator-always-on;
regulator-boot-on;
};
evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed";
regulator-name = "evm_1v8";
vin-supply = <&smps5_reg>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sw";
vin-supply = <&vsys_3v3>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3_sw>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vtt_fixed: fixedregulator-vtt {
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
};
};
&tpd12s015 {
compatible = "ti,dra7evm-tpd12s015";
pinctrl-names = "i2c", "ddc";
pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
ddc-i2c-bus = <&i2c2>;
mcasp-gpio = <&mcasp8>;
};
&dra7_pmx_core {
hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
pinctrl-single,pins = <
/* this pin is used as a GPIO via mcasp */
0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
>;
};
hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
pinctrl-single,pins = <
0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
>;
};
hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
pinctrl-single,pins = <
0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
mmc1_pins_default: pinmux_mmc1_default_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_hs: pinmux_mmc1_hs_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs: mmc2_pins_hs {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs200_1_8v: mmc2_pins_hs200_1_8v {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
};
&dra7_iodelay_core {
mmc1_iodelay_ddr50_rev11_conf: mmc1_iodelay_ddr50_rev11_conf {
pinctrl-single,pins = <
0x618 (A_DELAY(572) | G_DELAY(540)) /* CFG_MMC1_CLK_IN */
0x624 (A_DELAY(0) | G_DELAY(600)) /* CFG_MMC1_CMD_IN */
0x630 (A_DELAY(403) | G_DELAY(120)) /* CFG_MMC1_DAT0_IN */
0x63c (A_DELAY(23) | G_DELAY(60)) /* CFG_MMC1_DAT1_IN */
0x648 (A_DELAY(25) | G_DELAY(60)) /* CFG_MMC1_DAT2_IN */
0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
0x620 (A_DELAY(1525) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62c (A_DELAY(55) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc1_iodelay_ddr50_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
pinctrl-single,pins = <
0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
0x620 (A_DELAY(1271) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
0x624 (A_DELAY(229) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x630 (A_DELAY(850) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(20) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x63C (A_DELAY(468) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x648 (A_DELAY(466) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */
0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x654 (A_DELAY(399) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
pinctrl-single,pins = <
0x620 (A_DELAY(1063) | G_DELAY(17)) /* CFG_MMC1_CLK_OUT */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62c (A_DELAY(23) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(2) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
pinctrl-single,pins = <
0x620 (A_DELAY(600) | G_DELAY(400)) /* CFG_MMC1_CLK_OUT */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc2_iodelay_hs200_1_8v_rev11_conf: mmc2_iodelay_hs200_1_8v_rev11_conf {
pinctrl-single,pins = <
0x190 (A_DELAY(621) | G_DELAY(600)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(300) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(739) | G_DELAY(600)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(240) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(812) | G_DELAY(600)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(240) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(954) | G_DELAY(600)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(60) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(1340)| G_DELAY(420)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(935) | G_DELAY(600)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(525) | G_DELAY(600)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(767) | G_DELAY(600)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(225) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(565) | G_DELAY(600)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(60) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(969) | G_DELAY(600)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(180) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
mmc2_iodelay_hs200_1_8v_rev20_conf: mmc2_iodelay_hs200_1_8v_rev20_conf {
pinctrl-single,pins = <
0x190 (A_DELAY(274) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(162) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(401) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(73) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(465) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(115) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(633) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(47) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(935) | G_DELAY(280)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(621) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(183) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(467) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(262) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(46) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(684) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(76) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
pinctrl-single,pins = <
0x18c (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
0x1a4 (A_DELAY(274) | G_DELAY(240)) /* CFG_GPMC_A20_IN */
0x1b0 (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A21_IN */
0x1bc (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A22_IN */
0x1c8 (A_DELAY(514) | G_DELAY(360)) /* CFG_GPMC_A23_IN */
0x1d4 (A_DELAY(187) | G_DELAY(120)) /* CFG_GPMC_A24_IN */
0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
0x1ec (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A26_IN */
0x1f8 (A_DELAY(121) | G_DELAY(60)) /* CFG_GPMC_A27_IN */
0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(174) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(168) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(136) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(879) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(34) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(11) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
mmc2_iodelay_ddr_1_8v_rev20_conf: mmc2_iodelay_ddr_1_8v_rev20_conf {
pinctrl-single,pins = <
0x18c (A_DELAY(270) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
0x1a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_IN */
0x1b0 (A_DELAY(170) | G_DELAY(0)) /* CFG_GPMC_A21_IN */
0x1bc (A_DELAY(758) | G_DELAY(0)) /* CFG_GPMC_A22_IN */
0x1c8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */
0x1d4 (A_DELAY(81) | G_DELAY(0)) /* CFG_GPMC_A24_IN */
0x1e0 (A_DELAY(286) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
0x1ec (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_IN */
0x1f8 (A_DELAY(123) | G_DELAY(0)) /* CFG_GPMC_A27_IN */
0x360 (A_DELAY(346) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(55) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(422) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(642) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(128) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(395) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(623) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(54) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
ti,system-power-controller;
interrupt-controller;
#interrupt-cells = <2>;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
smps1-in-supply = <&vsys_3v3>;
smps2-in-supply = <&vsys_3v3>;
smps3-in-supply = <&vsys_3v3>;
smps4-in-supply = <&vsys_3v3>;
smps5-in-supply = <&vsys_3v3>;
ldo1-in-supply = <&vsys_3v3>;
ldo2-in-supply = <&vsys_3v3>;
ldo3-in-supply = <&vsys_5v0>;
ldo4-in-supply = <&vsys_5v0>;
ldo5-in-supply = <&vsys_3v3>;
tps65917_regulators: regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* GPU VDD_DSPEVE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps3_reg: smps3 {
/* VDD_CORE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDD_IVA */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDDS1V5 */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> VDA_PHY1_1V8 */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldo2_reg: ldo2 {
/* LDO2_OUT --> VDA_PHY2_1V8 */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-bypass;
regulator-always-on;
};
ldo3_reg: ldo3 {
/* VDA_USB_3V3 */
regulator-name = "ldo3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDD_SDIO_DV */
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
tps65917_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
lp87565: lp87565@60 {
compatible = "ti,lp87565-q1";
reg = <0x60>;
status = "disabled";
buck10-in-supply =<&vsys_3v3>;
buck23-in-supply =<&vsys_3v3>;
regulators: regulators {
buck10_reg: buck10 {
/*VDD_MPU*/
regulator-name = "buck10";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
buck23_reg: buck23 {
/* VDD_GPU*/
regulator-name = "buck23";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
};
};
pcf_lcd: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
};
i2c_p3_exp: &i2c2 {
status = "okay";
clock-frequency = <400000>;
pcf_hdmi: gpio@26 {
compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
vin6_brdmux: p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
ov10633@37 {
compatible = "ovti,ov10633";
reg = <0x37>;
mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
port {
onboardLI: endpoint {
remote-endpoint = <&vin1a>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
};
};
};
disp_ser: serializer@1b {
compatible = "ti,ds90uh925q";
reg = <0x1b>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo4_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev11_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev20_conf>;
pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
max-frequency = <192000000>;
pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev11_conf>;
pinctrl-3 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev20_conf>;
pinctrl-4 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev11_conf>;
pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>;
};
&oppdm_mpu {
vdd-supply = <&smps1_reg>;
};
&oppdm_dspeve {
vdd-supply = <&smps2_reg>;
};
&oppdm_gpu {
vdd-supply = <&smps2_reg>;
};
&oppdm_ivahd {
vdd-supply = <&smps4_reg>;
};
&oppdm_core {
vdd-supply = <&smps3_reg>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
&usb2_phy1 {
phy-supply = <&ldo3_reg>;
};
&usb2_phy2 {
phy-supply = <&ldo3_reg>;
};
&gpio7 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&mac {
status = "okay";
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <0>;
};
&davinci_mdio {
dp83867_0: ethernet-phy@1 {
compatible = "ethernet-phy-id1c.cb00";
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@0 {
compatible = "ethernet-phy-id0141.0dd0";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};
&mmu0_dsp1 {
status = "okay";
};
&mmu1_dsp1 {
status = "okay";
};
&mmu0_dsp2 {
status = "okay";
};
&mmu1_dsp2 {
status = "okay";
};
&mmu_ipu1 {
status = "okay";
};
&mmu_ipu2 {
status = "okay";
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_cma_pool>;
mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
timers = <&timer3>;
watchdog-timers = <&timer4>, <&timer9>;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_cma_pool>;
mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
timers = <&timer11>;
watchdog-timers = <&timer7>, <&timer8>;
};
&dcan1 {
status = "ok";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
&dsp1 {
status = "okay";
memory-region = <&dsp1_cma_pool>;
mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
timers = <&timer5>;
watchdog-timers = <&timer10>;
};
&dsp2 {
status = "okay";
memory-region = <&dsp2_cma_pool>;
mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
timers = <&timer6>;
watchdog-timers = <&timer13>;
};
&dss {
status = "okay";
vdda_video-supply = <&ldo5_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@lcd3 {
reg = <2>;
dpi_out3: endpoint {
data-lines = <24>;
};
};
};
};
&hdmi {
vdda-supply = <&ldo3_reg>;
};
&mcasp8 {
/* not used for audio. only the AXR2 pin is used as GPIO */
status = "okay";
};
video_in: &vin1a {
status = "okay";
endpoint@0 {
slave-mode;
remote-endpoint = <&onboardLI>;
};
};
&bb2d {
status = "okay";
};
please have a look,thanks very much
