This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3703: GPMC timing requirements

Part Number: AM3703

Hi, in the datasheet under Timing Requirements and Switching Specifications, for each of the timing parameters why is there not a case given for GpmcFCLKDivider = 3.  We are using this setting but now we aren't able to calculate the delay times because there isn't any note about GpmcFCLKDivider =3.  Please advise. Thanks.

Brandon

  • Hi Brandon,

    I don't know why these notes are enumerated out to GpmcFCLKDivider = 2 (div-by-3), but not GpmcFCLKDivider = 3 (div-by-4). Thanks for identifying that.

    Anyway these notes pretty much saying the same thing:
    The GPMC signals are all cycle based. The signals change state when the respective "ontime" or "offtime" bitfield in the register matches the cycle count, clocked by the internal GPMC_FCLK. An extra delay of a half GPMC_FCLK cycle can be applied to both ontime and offtime.
    The timings in the datasheet table are all relative to the external GPMC_CLK pin, mostly its rising edge (clkH). The external GPMC_CLK can be divided down from the internal GPMC_FCLK and it can be delayed by some multiple of GPMC_FCLK cycles.
    The GPMC signals are still launched on the same internal GPMC_FCLK rising edge, but the rising edge of the external GPMC_CLK may be moving around depending on GpmcFCLKDivider and ClkActivationTime. These notes communicate the offset from a GPMC_CLK rising edge to the GPMC signal transition, all possible places in the GPMC_CLK cycle.

    I think the logic can be extended to divide by 4. Lets try for WEn. Refer to the waveforms which highlight A and D below.
            
    (9) For WE falling edge (WE activated):
        – Case GpmcFCLKDivider = 3:
    A.        – I = 0.5 * WEExtraDelay * GPMC_FCLK (14) if ((WEOnTime – ClkActivationTime) is a multiple of 4)
    B.        – I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK (14) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 4)
    C.        – I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK (14) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 4)    
    D.        – I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK (14) if ((WEOnTime – ClkActivationTime – 3) is a multiple of 4)    
            
        For WE rising edge (WE deactivated):
        – Case GpmcFCLKDivider = 3:
            – I = 0.5 * WEExtraDelay * GPMC_FCLK (14) if ((WEOffTime – ClkActivationTime) is a multiple of 4)
            – I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK (14) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 4)
            – I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK (14) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 4)    
            – I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK (14) if ((WEOffTime – ClkActivationTime – 3) is a multiple of 4)    




    Regards,
    Mark