TMS320C5515: Lowering EMIF power supply for lower power drain.

citizen

Part Number: TMS320C5515

Hi,

On a current custom design based around the C5515, the DVDDEMIF is set to 3.3V and the EMIF is configured for use with a 3.3V compatible SDRAM from ISSI.

After having discussed with ISSI apps engineers regarding lowering memory power consumption, they advised lowering SDRAM power consumption through lower memory supply, and we all agree it is the best overall means to reduce SDRAM power drain.

If this is the case, from a board redesign perspective, is there anything else one would need to modify to the existing board, other than to set all processor DVDDEMIF power pins to a suitable 1.8V (or 2.5V), and then replacing the existing 3.3V SDRAM device with an equivalent lower voltage type ? I would envisage the register configuration to otherwise remain unchanged...

Thanks in advance for your advice, regards,

over 3 years ago

0 Rex Chang over 3 years ago

TI__Guru 50170 points

Hi, MM,

you should be able to simply populate a 1.8V/2.5V SDRAM and change the DVDDEMIF supply to match the voltage.

There are no register differences related to voltage. There may be register differences to accommodate any timing differences of the new memory.

On the C5515 EVM, there is a jumper to select DVDDEMIF to be either 1.8V or 3.3V – You could study the schematics to understand more details..

Keep in mind that the SDRAM clock can only be SYSCLK or SYSCLK/2 – this may force the system to use a SYSCLK that is slower than maximum. With DVDDEMIF = 1.8V, EM_SDCLK must be less than 60MHz.

Please refer to datasheet 5.9.2 EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported

• When CVDD =1.05 V, and DVDDEMIF = 3.3 V, 2.75 V, or 2.5 V, the max clock frequency on the EM_SDCLK pin is limited to 60 MHz (EM_SDCLK ≤ 60 MHz). Therefore, if SYSCLK ≤ 60 MHz, the EM_SDCLK can be configured as either SYSCLK or SYSCLK/2, but if SYSCLK > 60 MHz, the EM_SDCLK must be configured as SYSCLK/2.

• When DVDDEMIF = 1.8 V, regardless of the CVDD voltage, the clock frequency on the EM_SDCLK pin must be configured as SYSCLK/2 and ≤ 50 MHz.

As what's been said above, we have very limited collateral or resource beyond what you see in the product folder. You may search the E2E forum for archived posts of previous discussions which may help address your questions. For more info on TMS320C5515 support, please see the FAQ in

https://e2e.ti.com/support/processors/f/791/t/818771

Rex

0 citizen over 3 years ago in reply to Rex Chang

Expert 2770 points

Hi Rex,

Yes thanks, I did not account for the reduction in the SDRAM_CLK frequency.

We are considering 2.5V and 3.3V mainly with CVDD 1.3V unchanged. From this I can see in the datasheet that :

When CVDD = 1.3 V or 1.4 V, and DVDDEMIF = 3.3 V, 2.75 V, or 2.5 V, the max clock frequency on the
EM_SDCLK pin is limited to 100 MHz (EM_SDCLK ≤ 100 MHz). Therefore, if SYSCLK ≤ 100 MHz, the
EM_SDCLK can be configured either as SYSCLK or SYSCLK/2, but if SYSCLK > 100 MHz, the
EM_SDCLK must be configured as SYSCLK/2.

So it looks that for the DVDDEMIF = 2.5V we can keep the current 100MHz clock regardless ... However I did not see the memory supported in the datasheet. There is a small list in the SPRA719 appliation report, but is there somehting more recent perhaps, as some of the parts on the list are obsolete ??

Best Regards,

Micahel

0 Rex Chang over 3 years ago in reply to citizen

TI__Guru 50170 points

Hi, Michael,

The datasheet is at https://www.ti.com/lit/ds/symlink/tms320c5515.pdf?ts=1590615419437 and Section 5.9.2 "EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported".

As mentioned in my previous post, all info are in C5515 product folder. There isn't any update to it.

Rex

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TMS320C5515: Lowering EMIF power supply for lower power drain.