AM3517: ETB trace init

Be sure to check all clocks and clock status in the EMU_CM Module (section 4.12.1.10 of the TRM).  This should be all that is necessary to clock the emulation logic.  The EMU power domain status register seems to be missing from the TRM.  Can you check register 0x483071E4?   The two LSBs should be 0x3 to indicate the EMU power domain is ON.

I'm not aware of anything that specifically enables the ETM.  Please check the status bits in the registers mentioned above to see if the module is powered and clocked properly.

Regards,

James

Hi James,

Thank you for your quick reply.

0x483071E4 reads 0x103 for me. So EMU power domain appears to be on.

0x48005140 reads 0x02030A50 which looks like reset values except the DIV_DPLL3.

What is odd is that I can write and read ETB registers at 0x5401B000 from CPU space (AHB and APB space do not work here either).

But both TPIU (0x54019000) and ETM (0x54010000), can't be read or written at all. Neither from CPU space, AHB or APB.

So either I use the wrong addresses/APs for ETM and TPIU or they are not clocked and that is why they are not readable.

Can you confirm on which addresses in which memory space the ETM and TPIU should be reachable?

Do you have information on how TI tested the ETB trace functionality of the chip? Are there any scripts or example setups available/known?

Best regards,

Nino

Nino, i looked back at some specs to confirm

ETM 0x54010000

TPIU 0x54019000

ETB 0x5401B000

You might be running into a security issue where these modules are only accessible with the emulator.  

In the previous thread, you were having trouble accessing the GENERAL_WKUP (0x48002a60) registers.  Is this still the case?  Can you read SEC_TAP (0x48002a60) register or SEC_DAP (0x48002a7C) register? 

What is the value of SEC_CTRL register (0x480002B0)? Bit3 will determine if you have write access to the GENERAL_WKUP region.

REgards,

James

Hi James,

>>You might be running into a security issue where these modules are only accessible with the emulator. 

What is the emulator in this context? My external debug probe or something else TI related?

I checked the mentioned registers once more.

I read 0x00000000 from both but can only write to the SEC_DAP register. The SEC_TAP register is not writable for me under no circumstances. I even tried all different memory spaces with no success.

What needs to be done for the SEC_TAP to be writable, or is this simply a chip limitation? Can this somehow be lifted?

For reference the print on my chip reads: XAM3517ZCN

Best regards,

Nino

Nino, i think on a GP device, which you have, you may be running into access restrictions which do not allow you to read or modify these registers.  Your Segger probe may also be restricting you, I'm not sure as i have not used this probe.

When accessing the registers, is the ARM in supervisor or one of the privileged mode?

Regards,

James   

Hi James,

All accesses via DAP by the debug probe are done in privileged mode. Otherwise other basic debug features would also not be working.

Is there a way to find out if this is a access restriction issue? If yes what steps do you recommend for verification?

If it is such an issue what steps do you recommend to work around it?

Is there an evaluation board available with no such restrictions?

Best regards,

Nino

Hi Nino, I'm not sure what the problem is.  Have you tried a TI EVM with a TI JTAG Debugger to see if you have the same issue?  This would confirm access restrictions.  I will try to ask around.

James

Hi James,

the problem is I can't write nor read from the ETM to enable ETB tracing. Only the ETB is accessible.

Everything else were suggestions by you to test random registers which I did without much new information and I still can't access the ETM.

"Have you tried a TI EVM with a TI JTAG Debugger to see if you have the same issue? " This would be something that you could try assuming you have that hardware no?

All I want is that with a J-Link to be able to do ETB trace on this board. I do not care if other probes might work.

If you can't provide me with the necessary steps to do this please put me in contact with someone who can.

As already said, the initialization we are using works perfectly fine on other Cortex-A and Cortex-R targets. It is only the TI AM35xx series making these problems which points to a target specific issue or extra steps necessary that are not documented.

Nino,

I am not entirely sure if ETM is connected or working on the AM35xx devices (based on the old OMAP3530 devices).

Would you be interested in getting the specifications to perform further analysis? If so, please accept my friend request so I can start the process of making this documentation available. 

Regards,

Rafael

Hi Rafael,

Is there anyone at TI who is sure if and how the ETM is implemented?

desouza said:

Would you be interested in getting the specifications to perform further analysis? If so, please accept my friend request so I can start the process of making this documentation available. 

That would be great. I accepted the request.

Best regards,

Nino