AM5728: Issue adapting MCASP_Audio_evmAM572x_c66ExampleProject for IDK

What is the value being read from the CM_L4PER2_MCASP3_CLKCTRL register (address 0x4A00 9868)?

0x30002

Do you have a TI debugger (e.g. XDS100v2, XDS110, etc.)?  If so, you can capture a register dump of the complete clock tree.  That will help us understand why that clock isn't turning on.

You should download the following script:

https://git.ti.com/cgit/sitara-dss-files/am57xx-dss-files/plain/am57xx-ctt.dss?h=master

Directions on how to run it can be found here:

http://git.ti.com/sitara-dss-files/am57xx-dss-files/blobs/master/README

You can rename the generated *.rd1 file as *.txt and attach to your response (or zip it and attach).

Do you have a second clock in your system?  In other words, are you using only the 20 MHz main clock hooked up to SYS_CLK1 or do you also have another clock hooked up to SYS_CLK2?

What I think might be the issue is that currently you have configured CM_CLKSEL_ABE_PLL_SYS[0] to a value of 1 (SYS_CLK2).  If you don't have anything connected to that clock then you end up without an AUXCLK for the McASP which is a critical clock.  That's likely why it's not turning on correctly.

We haven't made any modifications to the IDK in terms of clocks (except for MCASP_ACLKR coming from the ADC, as the AM5728 is running as a slave). Is the presence of SYS_CLK2 something which is different on the general purpose EVM as opposed to the IDK?

Great! So the McASP device should work properly with CM_CLKSEL_ABE_PLL_SYS[0] set to 0?

Thanks!

I am getting past this initialization stage now, but am getting an abort when calling mcaspCreateChan(). Specifically, stepping into the driver, an assert is failing when calling:

    /* start AHCLKR                                                           */
    mcaspBitSetGblRCtl(instHandle, (uint32_t) MCASP_GBLCTLR_RHCLKRST_MASK);

It seems to be a timeout waiting for another register value to be updated

What is the value of the MCASP_AHCLKRCTL register (address 0x4846 8074)?

0x00008000

Can you please snip a few lines of code so I see a line or two before and after the problematic code?

Also, can you please provide the values for these registers:

• MCASP_ACLKRCTL, 0x4846 8070
• MCASP_ACLKXCTL. 0x4846 80B0

Thanks,
Brad

MCASP_ACLKRCTL = 0x20

MCASP_ACLKXCTL = 0x60

The relevant calls in the application code leading up to the issue are:

Mcasp_socGetInitCfg(MCASP_NUM, &hwInfo);

hwInfo.dmaHandle = McaspApp_edmaInit(&hwInfo);

Mcasp_socSetInitCfg(MCASP_NUM, &hwInfo);

...

status = mcaspBindDev(&hMcaspDev, MCASP_NUM, &mcaspParams);
    if((status != MCASP_COMPLETED) || (hMcaspDev == NULL))
    {
        MCASP_log("mcaspBindDev for McASP Failed\n");
        abort();
    }

    status = mcaspCreateChan(&hMcaspRxChan, hMcaspDev,
                             MCASP_INPUT,
                             &mcasp_chanparam[0],
                             mcaspAppCallback, NULL);

The abort happens within the driver implementation of mcaspCreateChan:

...

    /* Reset RHCLKRST, RCLKRST, RSRCLR in GBLCTL                              */
    mcaspBitRemoveGblRCtl(
        instHandle,
        ~((uint32_t) MCASP_GBLCTLR_RHCLKRST_MASK
          | (uint32_t) MCASP_GBLCTLR_RCLKRST_MASK
          | (uint32_t) MCASP_GBLCTLR_RSRCLR_MASK));

    /* Configure it completely before starting the clocks                     */
    /* Configure RTDM register                                                */
    McASPRxTimeSlotSet(instHandle->hwInfo.regs, rcvData->tdm);

    /* Configure RXCLKCHK register                                            */
    McASPRxClkCheckRegWrite(instHandle->hwInfo.regs,
                            rcvData->clk.clkChk);

    McASPRxClkPolaritySet(instHandle->hwInfo.regs,
                          (rcvData->clk.clkSetupClk &
                           (uint32_t) MCASP_ACLKRCTL_CLKRP_MASK));

    McASPRxHFClkPolaritySet(instHandle->hwInfo.regs,
                            ((rcvData->clk.clkSetupHiClk &
                              (uint32_t) MCASP_AHCLKRCTL_HCLKRP_MASK) <<
                             MCASP_AHCLKRCTL_HCLKRP_SHIFT));

    McASPRxClkCfg(instHandle->hwInfo.regs,
                  ((rcvData->clk.clkSetupClk &
                    (uint32_t) MCASP_ACLKRCTL_CLKRM_MASK) |
                   (rcvData->clk.clkSetupHiClk &
                    (uint32_t) MCASP_AHCLKRCTL_HCLKRM_MASK)),
                  ((rcvData->clk.clkSetupClk &
                    (uint32_t) MCASP_ACLKRCTL_CLKRDIV_MASK) >>
                   MCASP_ACLKRCTL_CLKRDIV_SHIFT),
                  ((rcvData->clk.clkSetupHiClk &
                    (uint32_t) MCASP_AHCLKRCTL_HCLKRDIV_MASK) >>
                   MCASP_AHCLKRCTL_HCLKRDIV_SHIFT));
    /* Sequence of start: starting hclk first                                 */
    /* start AHCLKR                                                           */
    mcaspBitSetGblRCtl(instHandle, (uint32_t) MCASP_GBLCTLR_RHCLKRST_MASK);

...

 void mcaspBitSetGblRCtl(const Mcasp_Object *instHandle,uint32_t bitMaskVal)
{
    uint32_t timeout = Mcasp_GBLCTL_TIMEOUT;
    Bool   isTask  = (Bool)FALSE;
    uint32_t tempVal1 = 0x00;
    uint32_t tempVal2 = 0x00;

    if(NULL != instHandle)
    {
    tempVal1 = McASPGlobalCtlGet(instHandle->hwInfo.regs);
    tempVal2 = McASPRxGlobalCtlGet(instHandle->hwInfo.regs);
    /* If already this bit is set then don't set again                        */
    if ((tempVal1 & bitMaskVal) != bitMaskVal)
    {
        if (FALSE == instHandle->RcvObj.isDmaDriven)
        {
           Mcasp_disableInterrupt(instHandle->RcvObj.cpuEventNum,instHandle->RcvObj.intNum);
        }

        tempVal2 |= bitMaskVal;
        McASPRxGlobalCtlSet(instHandle->hwInfo.regs, tempVal2);
        tempVal1 = McASPGlobalCtlGet(instHandle->hwInfo.regs);

        while (((tempVal1 & bitMaskVal) !=
                bitMaskVal) && (timeout > 0U))
        {
            /* decrement the timeout count                                    */
            timeout--;

            isTask = (Bool)(Osal_getThreadType()==Osal_ThreadType_Swi);

            /* wait for 1 tick only if called from a task context             */
            if (TRUE == isTask)
            {
                Osal_delay(1);
            }
            tempVal1 = McASPGlobalCtlGet(instHandle->hwInfo.regs);
        }

        assert(0U != timeout);

Please capture a new clock tree register dump so I can review further.

Samuel -- On second thought I don't think I need the clock tree dump.  Instead can you please tell me the value of this register:

CM_L4PER2_CLKSTCTRL, 0x4A00 98FC

If the lower nibble is anything besides 2 please try setting it to 2.

Also please look at this register:

CM_L4CFG_CLKSTCTRL, 0x4A00 8D00

If the lower nibble is non-zero, please set it to zero.  Please let me know the values of those registers before and after any changes.

Thanks!

Brad

Hi Brad,

I actually got past this issue earlier today by reinstalling the latest SDK version. What I found odd, is it is working with CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG still set for SYS_CLK2, even though I had to switch CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG to SYS_CLK1 because there is no SYS_CLK2 on the IDK. If I change CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG for SYS_CLK1 I still get the abort in the same place.

        HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG, \
                CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL, \
                CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK1);

...

        HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG, \
                CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL, \
                CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_SYS_CLK2);

Thanks for your help, Brad. I still don't have my code fully up and running yet, but I'm not "stuck" anymore.

Samuel,

Thanks for the update.  I have closed this thread.  If you run into further issues please start a new thread.

Thanks!
Brad