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AM5728: Issue adapting MCASP_Audio_evmAM572x_c66ExampleProject for IDK

Part Number: AM5728

I am working with an AM5728 IDK which has been modified to connect to an adc over McASP4. I am trying to use the MCASP_Audio_evmAM572x_c66ExampleProject as a starting point and modify it to run MCASP4 as a slave to get data from the ADC.

When I run my project on the IDK it is getting stuck in an infinite while loop in the McASP3_Enable() function. I had converted this to McASP4_Enable and it wasn't working so I tired running the original McASP3_Enable and it gets stuck in the same place. This is where it gets stuck:

        /* McASP3 Module Control */
        HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG, \
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE, \
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE);
        while (HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG) != \
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE) ;

I had run this example project successfully on an evmAM572x before modifying it to run as a slave on McASP4. The point in the code where it gets stuck is before it reaches most of my changes. Is there something inherently different about the IDK compared with the EVM which could be causing this issue?

  • What is the value being read from the CM_L4PER2_MCASP3_CLKCTRL register (address 0x4A00 9868)?

  • Do you have a TI debugger (e.g. XDS100v2, XDS110, etc.)?  If so, you can capture a register dump of the complete clock tree.  That will help us understand why that clock isn't turning on.

    You should download the following script:

    https://git.ti.com/cgit/sitara-dss-files/am57xx-dss-files/plain/am57xx-ctt.dss?h=master

    Directions on how to run it can be found here:

    http://git.ti.com/sitara-dss-files/am57xx-dss-files/blobs/master/README

    You can rename the generated *.rd1 file as *.txt and attach to your response (or zip it and attach).

  • am57xx-ctt_2020-06-05_170338.txt
    DeviceName AM572x_SR2.0_SR1.1
    0x4a005560 0x00000002
    0x4ae06118 0x00000001
    0x4a008920 0x00000001
    0x4ae06190 0x00000000
    0x4a0052e4 0x0000aa03
    0x4ae061c8 0x00000000
    0x4ae06174 0x00000000
    0x4a009848 0x00030000
    0x4ae07888 0x00030000
    0x4a005228 0x00000208
    0x4a002360 0x00000000
    0x4a0051ec 0x0080c809
    0x4a009770 0x00000001
    0x4a009908 0x00030000
    0x4ae07a04 0x00000001
    0x4a005254 0x00000000
    0x4ae06154 0x00000000
    0x4a009858 0x00030000
    0x4a00521c 0x00010a04
    0x4ae061bc 0x00000000
    0x4a009750 0x00000002
    0x4a009780 0x00000001
    0x4a0097a8 0x00000002
    0x4a008778 0x00000001
    0x4a009328 0x03040002
    0x4a005234 0x00000007
    0x4a005244 0x00000201
    0x4a0052b8 0x00000204
    0x4a009388 0x00070000
    0x4a005130 0x00000002
    0x4a005154 0x00000205
    0x4a0098e8 0x00030000
    0x4a008e40 0x00030000
    0x4a005550 0x00030000
    0x4a0093e8 0x00030000
    0x4ae07830 0x00000002
    0x4a00516c 0x0081f409
    0x4a009620 0x00030000
    0x4a005520 0x01000001
    0x4a005580 0x00030000
    0x4a008210 0x0000000f
    0x4a008e28 0x00000001
    0x4ae061a0 0x00000000
    0x4a009738 0x00000002
    0x4a005248 0x00000003
    0x4a009800 0x00030000
    0x4a0052c8 0x0000020a
    0x4a0052d8 0x00000007
    0x4a005140 0x0000003e
    0x4a0052e8 0x00000002
    0x4a0098a8 0x00030000
    0x4a005720 0x00070000
    0x4ae06180 0x00000000
    0x4a009798 0x00030000
    0x4ae061c0 0x00000000
    0x4a0051e0 0x00000007
    0x4ae06108 0x00000000
    0x4a0051f0 0x00000001
    0x4ae07840 0x00000002
    0x4ae06170 0x00000000
    0x4a009200 0x00000003
    0x4a0097d8 0x00000002
    0x4a005210 0x00000007
    0x4a0098f0 0x00030000
    0x4ae07838 0x00000001
    0x4a005220 0x00000202
    0x4a009868 0x00030002
    0x4a008158 0x00000203
    0x4a00519c 0x00000000
    0x4a0086a0 0x00000000
    0x4ae061d4 0x00000000
    0x4ae06138 0x00000000
    0x4ae061c4 0x00000000
    0x4a0051f4 0x00000001
    0x4ae06114 0x00000000
    0x4a008e50 0x02000001
    0x4a009760 0x00000001
    0x4a009720 0x00040002
    0x4ae061d0 0x00000000
    0x4a009878 0x00030000
    0x4a00814c 0x00006004
    0x4a008200 0x00000007
    0x4a005160 0x00000007
    0x4a0093b0 0x00070000
    0x4a005170 0x00000201
    0x4ae061d8 0x00000000
    0x4a009120 0x00043f02
    0x4a008b30 0x00000001
    0x4a0052c0 0x00000228
    0x4a0051ac 0x0000e903
    0x4ae061a8 0x00000000
    0x4a00815c 0x00000204
    0x4a005568 0x00000002
    0x4a0093d0 0x08000002
    0x4a009820 0x00000002
    0x4a009220 0x00070000
    0x4a002534 0x00000000
    0x4a009020 0x00000001
    0x4a0098d0 0x00030000
    0x4a0056e0 0x00070000
    0x4a0093e0 0x00030000
    0x4a009130 0x00070000
    0x4a009850 0x00000002
    0x4a005158 0x00000204
    0x4a005764 0x00000001
    0x4a009788 0x00030000
    0x4a008160 0x00000204
    0x4ae07878 0x00030000
    0x4a009030 0x00000001
    0x4a009890 0x00030000
    0x4a009870 0x00030000
    0x4a0097f0 0x00000002
    0x4ae06194 0x00000000
    0x4a009340 0x00070000
    0x4a0097c4 0x00030000
    0x4a009810 0x00000001
    0x4a0097b0 0x00000002
    0x4a0051dc 0x00000000
    0x4a008780 0x00000001
    0x4a005144 0x00000005
    0x4a008164 0x00000002
    0x4a008140 0x00000007
    0x4a0097c8 0x00000002
    0x4a008150 0x00000804
    0x4ae0610c 0x00000000
    0x4a0098c8 0x00030000
    0x4ae06198 0x00000000
    0x4ae06168 0x00000000
    0x4ae06184 0x00000000
    0x4ae06148 0x00000000
    0x4a0051a0 0x00000007
    0x4a0051b0 0x00000203
    0x4ae0619c 0x00000000
    0x4a0056a0 0x00070000
    0x4a009740 0x00000002
    0x4a00821c 0x00000000
    0x4a009808 0x00030000
    0x4a009728 0x00000002
    0x4a005290 0x00000000
    0x4ae061cc 0x00000000
    0x4a005558 0x00000002
    0x4ae0612c 0x00000000
    0x4ae06178 0x00000000
    0x4a005620 0x00000001
    0x4a009830 0x00000002
    0x4a00818c 0x04000000
    0x4a00820c 0x0402ee09
    0x4a008f28 0x00000001
    0x4a002544 0xf757fdc0
    0x4a009898 0x00030000
    0x4ae061b0 0x00000000
    0x4a009840 0x00000002
    0x4a009768 0x00000001
    0x4a009904 0x00030000
    0x4a00515c 0x00000006
    0x4ae061b8 0x00000000
    0x4a0052bc 0x0000020a
    0x4a0093b8 0x00070000
    0x4a008b38 0x00000001
    0x4ae061b4 0x00000000
    0x4a009778 0x00000001
    0x4a005570 0x00000002
    0x4a0097a0 0x00000002
    0x4a0052a4 0x00000000
    0x4a005660 0x00070000
    0x4ae06110 0x00000002
    0x4a009828 0x00000002
    0x4ae06164 0x00000000
    0x4a008b40 0x00000000
    0x4ae06160 0x00000000
    0x4ae0615c 0x00000000
    0x4ae06158 0x00000000
    0x4a009028 0x00000001
    0x4a0098e0 0x00030000
    0x4a005284 0x00000005
    0x4a005294 0x00000001
    0x4a009330 0x00040002
    0x4ae0614c 0x00000000
    0x4a005420 0x00000001
    0x4a0093f0 0x00070000
    0x4ae06150 0x00000000
    0x4a008180 0x00000005
    0x4a0052b4 0x0000fa04
    0x4a008190 0x00000001
    0x4a00512c 0x00010a04
    0x4a005100 0x00000110
    0x4a0097f8 0x00030000
    0x4a008f20 0x00000001
    0x4ae0618c 0x00000000
    0x4a0098a0 0x00030000
    0x4ae061e0 0x00000000
    0x4a0098c0 0x00030000
    0x4a009790 0x00030000
    0x4a009838 0x05000002
    0x4a009818 0x00000001
    0x4a0097b8 0x00000002
    0x4a008728 0x00000001
    0x4a0097d0 0x00000002
    0x4a008e20 0x00000001
    0x4a0098f8 0x00030000
    0x4ae07880 0x00030000
    0x4ae0616c 0x00000000
    0x4a009860 0x00030000
    0x4ae061ac 0x00000000
    0x4a0098b0 0x00030000
    0x4a0052c4 0x00000208
    0x4a00513c 0x00000204
    0x4ae06120 0x00000000
    0x4a009748 0x00000002
    0x4ae06144 0x00000000
    0x4a005578 0x00030000
    0x4a005240 0x00009604
    0x4a009718 0x00040002
    0x4a009730 0x00000002
    0x4a0052a8 0x00000007
    0x4a005120 0x00000007
    0x4a0086b0 0x00000000
    0x4a009910 0x00001f02
    0x4ae06188 0x00000000
    0x4ae061a4 0x00000000
    0x4ae06128 0x00000000
    

  • Do you have a second clock in your system?  In other words, are you using only the 20 MHz main clock hooked up to SYS_CLK1 or do you also have another clock hooked up to SYS_CLK2?

    What I think might be the issue is that currently you have configured CM_CLKSEL_ABE_PLL_SYS[0] to a value of 1 (SYS_CLK2).  If you don't have anything connected to that clock then you end up without an AUXCLK for the McASP which is a critical clock.  That's likely why it's not turning on correctly.

  • We haven't made any modifications to the IDK in terms of clocks (except for MCASP_ACLKR coming from the ADC, as the AM5728 is running as a slave). Is the presence of SYS_CLK2 something which is different on the general purpose EVM as opposed to the IDK?

  • Yes, this is a difference between the EVM and IDK.

    • EVM OSC1 (SYS_CLK2) = 22.5792 MHz
    • IDK OSC1 (SYS_CLK2) = ground

    Both boards connect a 20 MHz crystal to OSC0 (SYS_CLK1).  The bit I mentioned is likely your issue.

  • Great! So the McASP device should work properly with CM_CLKSEL_ABE_PLL_SYS[0] set to 0?

    Thanks!

  • I am getting past this initialization stage now, but am getting an abort when calling mcaspCreateChan(). Specifically, stepping into the driver, an assert is failing when calling:

        /* start AHCLKR                                                           */
        mcaspBitSetGblRCtl(instHandle, (uint32_t) MCASP_GBLCTLR_RHCLKRST_MASK);

    It seems to be a timeout waiting for another register value to be updated

  • What is the value of the MCASP_AHCLKRCTL register (address 0x4846 8074)?

  • Can you please snip a few lines of code so I see a line or two before and after the problematic code?

    Also, can you please provide the values for these registers:

    • MCASP_ACLKRCTL, 0x4846 8070
    • MCASP_ACLKXCTL. 0x4846 80B0

    Thanks,
    Brad

  • MCASP_ACLKRCTL = 0x20

    MCASP_ACLKXCTL = 0x60

    The relevant calls in the application code leading up to the issue are:

    Mcasp_socGetInitCfg(MCASP_NUM, &hwInfo);

    hwInfo.dmaHandle = McaspApp_edmaInit(&hwInfo);

    Mcasp_socSetInitCfg(MCASP_NUM, &hwInfo);

    ...

    status = mcaspBindDev(&hMcaspDev, MCASP_NUM, &mcaspParams);
        if((status != MCASP_COMPLETED) || (hMcaspDev == NULL))
        {
            MCASP_log("mcaspBindDev for McASP Failed\n");
            abort();
        }

        status = mcaspCreateChan(&hMcaspRxChan, hMcaspDev,
                                 MCASP_INPUT,
                                 &mcasp_chanparam[0],
                                 mcaspAppCallback, NULL);

    The abort happens within the driver implementation of mcaspCreateChan:

    ...

        /* Reset RHCLKRST, RCLKRST, RSRCLR in GBLCTL                              */
        mcaspBitRemoveGblRCtl(
            instHandle,
            ~((uint32_t) MCASP_GBLCTLR_RHCLKRST_MASK
              | (uint32_t) MCASP_GBLCTLR_RCLKRST_MASK
              | (uint32_t) MCASP_GBLCTLR_RSRCLR_MASK));

        /* Configure it completely before starting the clocks                     */
        /* Configure RTDM register                                                */
        McASPRxTimeSlotSet(instHandle->hwInfo.regs, rcvData->tdm);

        /* Configure RXCLKCHK register                                            */
        McASPRxClkCheckRegWrite(instHandle->hwInfo.regs,
                                rcvData->clk.clkChk);

        McASPRxClkPolaritySet(instHandle->hwInfo.regs,
                              (rcvData->clk.clkSetupClk &
                               (uint32_t) MCASP_ACLKRCTL_CLKRP_MASK));

        McASPRxHFClkPolaritySet(instHandle->hwInfo.regs,
                                ((rcvData->clk.clkSetupHiClk &
                                  (uint32_t) MCASP_AHCLKRCTL_HCLKRP_MASK) <<
                                 MCASP_AHCLKRCTL_HCLKRP_SHIFT));

        McASPRxClkCfg(instHandle->hwInfo.regs,
                      ((rcvData->clk.clkSetupClk &
                        (uint32_t) MCASP_ACLKRCTL_CLKRM_MASK) |
                       (rcvData->clk.clkSetupHiClk &
                        (uint32_t) MCASP_AHCLKRCTL_HCLKRM_MASK)),
                      ((rcvData->clk.clkSetupClk &
                        (uint32_t) MCASP_ACLKRCTL_CLKRDIV_MASK) >>
                       MCASP_ACLKRCTL_CLKRDIV_SHIFT),
                      ((rcvData->clk.clkSetupHiClk &
                        (uint32_t) MCASP_AHCLKRCTL_HCLKRDIV_MASK) >>
                       MCASP_AHCLKRCTL_HCLKRDIV_SHIFT));
        /* Sequence of start: starting hclk first                                 */
        /* start AHCLKR                                                           */
        mcaspBitSetGblRCtl(instHandle, (uint32_t) MCASP_GBLCTLR_RHCLKRST_MASK);

    ...

     void mcaspBitSetGblRCtl(const Mcasp_Object *instHandle,uint32_t bitMaskVal)
    {
        uint32_t timeout = Mcasp_GBLCTL_TIMEOUT;
        Bool   isTask  = (Bool)FALSE;
        uint32_t tempVal1 = 0x00;
        uint32_t tempVal2 = 0x00;

        if(NULL != instHandle)
        {
        tempVal1 = McASPGlobalCtlGet(instHandle->hwInfo.regs);
        tempVal2 = McASPRxGlobalCtlGet(instHandle->hwInfo.regs);
        /* If already this bit is set then don't set again                        */
        if ((tempVal1 & bitMaskVal) != bitMaskVal)
        {
            if (FALSE == instHandle->RcvObj.isDmaDriven)
            {
               Mcasp_disableInterrupt(instHandle->RcvObj.cpuEventNum,instHandle->RcvObj.intNum);
            }

            tempVal2 |= bitMaskVal;
            McASPRxGlobalCtlSet(instHandle->hwInfo.regs, tempVal2);
            tempVal1 = McASPGlobalCtlGet(instHandle->hwInfo.regs);

            while (((tempVal1 & bitMaskVal) !=
                    bitMaskVal) && (timeout > 0U))
            {
                /* decrement the timeout count                                    */
                timeout--;

                isTask = (Bool)(Osal_getThreadType()==Osal_ThreadType_Swi);

                /* wait for 1 tick only if called from a task context             */
                if (TRUE == isTask)
                {
                    Osal_delay(1);
                }
                tempVal1 = McASPGlobalCtlGet(instHandle->hwInfo.regs);
            }

            assert(0U != timeout);

  • Please capture a new clock tree register dump so I can review further.

  • Samuel -- On second thought I don't think I need the clock tree dump.  Instead can you please tell me the value of this register:

    CM_L4PER2_CLKSTCTRL, 0x4A00 98FC

    If the lower nibble is anything besides 2 please try setting it to 2.

    Also please look at this register:

    CM_L4CFG_CLKSTCTRL, 0x4A00 8D00

    If the lower nibble is non-zero, please set it to zero.  Please let me know the values of those registers before and after any changes.

    Thanks!

    Brad

  • Hi Brad,

    I actually got past this issue earlier today by reinstalling the latest SDK version. What I found odd, is it is working with CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG still set for SYS_CLK2, even though I had to switch CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG to SYS_CLK1 because there is no SYS_CLK2 on the IDK. If I change CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG for SYS_CLK1 I still get the abort in the same place.

            HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG, \
                    CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL, \
                    CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK1);

    ...

            HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG, \
                    CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL, \
                    CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_SYS_CLK2);

    Thanks for your help, Brad. I still don't have my code fully up and running yet, but I'm not "stuck" anymore.

  • Samuel,

    Thanks for the update.  I have closed this thread.  If you run into further issues please start a new thread.

    Thanks!
    Brad