Hi All,
From the picture, the capacitor one is end is connected to VDDQ_1V5. Why it is not connected to ground?
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Hi All,
From the picture, the capacitor one is end is connected to VDDQ_1V5. Why it is not connected to ground?
Hareesh,
The CK and address circuits are different. Whereas CK is 50-Ohm AC coupled to VDD_DDR (not using VTT), ADDR is 50-Ohm DC terminated to VTT. The caps on address are not really termination; they are for decoupling of the VTT net of the address bus. Since VTT is a mid-rail net (= VDD_DDR/2), it can be decoupled either to VSS or to VDD_DDR.
The approach shown has been fully validated by TI and if you're designing a new system is the recommended approach for DM8148 to interface to DDR.
Regards,
Kyle