Other Parts Discussed in Thread: DRA829
I have some concerns on the JTAG implementation in my design as the DRA829 has the TDI,TDO, and TMS signals at 1.8V and EMU, EMU1, TRSTn, and TCK are all at 3.3V.
I am using a MIPI60 connector (1.8V level) for an external emulator as well as an FT4232H (3.3V level) for an alternate JTAG source. Currently, if the MIPI60 is attached, then the EMU, TRSTn, and TCK signals will be level shifted to 3.3V. Is the added delay to TCK ok if the same delay is not seen by the data lines?
For the FTDI JTAG, I have to level shift TDI, TDO, and TMS to 3.3V. Now there will be a delay on the data lines but not on TCK. Is this an issue?