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TMS320C6727B: C6654 using SYSCLKOUT as a clock

Part Number: TMS320C6727B

Hi Team,

My customer is wondering:

On the C6654, are there any issues with using the SYSCLKOUT pin (it is connected to SYSCLK7) as a clock so the EMIF16 lines (clocked with SYSCLK7) can be treated as a synchronous bus?

They want to attach the EMIF16 lines to an FPGA  and sending the SYSCLKOUT to the FPGA would help with metastability.



  • Hello Connie,

    The EMIF 16 is asynchronous only and doesn't include a synchronous clock out or clock in.  There is no timing correlation between the clock output on SYSCLKOUT and the EMIF16 interface so we can't provide any setup or hold times from the clock edges. SYSCLKOUT is provided as a test signal to determine the frequency programmed into the system PLL. 

    An external device must meet the setup and hold times defined in the data manual since only the CS, data and either OE or WE signals are available outside the part.