Dear TI team,
I believe the clock tree tool (I tested 1.0.0.8 and 1.0.0.9) misinterprets the CTRLMMR_WKUP_MAIN_SYSCLK_CTRL.SYSCLK0_GATE bit.
The documentation for this bit says "When set, gates off SYSCLK0 (CLK1) output of the MAIN PLL Controller". I take that to mean that the output clock is enabled when the bit is cleared, and the clock gets disabled by setting this bit.
The clock tree tool appears to use an inverse interpretation, i.e. it assumes that the clock is enabeld only when this bit is set. See the following two screenshots:
On the first screenshot the SYSLK0_GATE bit is 0, and the CTT assumes that the output from PLLCTR0 is disabled. On the second screenshot the bit is set, and the CTT displays the resulting frequencies.
Can you confirm that the gate bit means "disabled when set", or am I missing something?
I believe CTT operation is mostly (completely?) driven by the XMLFiles, but I couldn't find an example of a "negated" switch. Is the CTT_Model_definition.xsd or some other documentation for the XML models available somewhere?
Regards,
Dominic