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CCS/TMS320C5505: The maximum operating frequency of EM_SDCLK

UNA
Mastermind 7980 points
Part Number: TMS320C5505

Tool/software: Code Composer Studio

Hi,

The TMS320C5505 data sheet shows that the maximum operating frequency of EM_SDCLK is 50 MHz when DVDDEMIF = 1.8 V, as shown in the figure below.
Does this mean that the operating frequency of the DSP needs to be less than 100 MHz?

This provision seems to have been added from Rev. F of the DS, what is the reason for this condition being added?

My customer adopted the C5505 before this requirement was stipulated. There is mSDRAM connected to EMIF and it is run on EMIF_CLK of 100Mhz and above.
This is why it is a major problem. So, I would like to clarify why this condition has been added.


Best Regards,
H.U

  • 0
    TI__Guru 50170 points

    Hi, H.U.

    Sorry for the slow response.

    We do not have any collateral or resource beyond what you see in the product folder. You may search the E2E forum for archived posts of previous discussions which may help address your questions. For more info on TMS320C5505 support, please see the FAQ in 

       https://e2e.ti.com/support/processors/f/791/t/818771

    I tried to reach out to other team to see if anyone can answer your query but haven't heard any feedback yet. I regret the inconvenience and lack of guidance here. If I hear back any, the answer will be posted.

    Rex

  • 0 in reply to Rex Chang
    Mastermind 7980 points

    Hi Rex,

    I understand the TI support stance on the C5505.
    However, this issue will have a significant impact on customers' future adoption of the C5505.
    So I need more information on the details.

    Best Regards,
    H.U

  • 0 in reply to UNA
    TI__Guru 50170 points

    Hi, H.U,

    Just FYI that we are consulting this issue internally, but have not heard back yet. I'll post the info as soon as I hear back from the expert.

    Rex

  • 0
    TI__Guru* 78395 points

    Hello H.U-san

    The limitation on c5505 EMIF clock rate for 1.8V has been in the datasheet since 2013 (rev F version). It is unfortunate that the customer did not notice this change and adjust the design accordingly.

    With DVDDEMIF @ 1.8V, the EMIF CLK pin is limited to 50MHz due to EMIF I/O cell limitation at 1.8V.  

     If DVDDEMIF @ 1.8V, then EMIF CLK pin is limited to 50MHz (CVDD @ 1.05V, 1.3V, 1.4V) If DVDDEMIF @ 2.75V or 3.3V, then EMIF CLK pin is limited to 75MHz (CVDD @ 1.05V) or 100MHz (CVDD @ 1.3V or 1.4V)

     Because the EMIF CLK divider only allows /1 or /2, the SYSCLK is also limited in order to meet the EMIF CLK limitation.

     This limitation exists across all of our c55x devices (C5505/15/17 etc).  I do not have any further details on this I/O cell limitation - and I am not sure we can support any further in-depth queries on this. We recommend customer to adjust their design as best as they can to adhere to the datasheet specifications. 

    Let us know what are the next steps to help you close with your customer.

    Regards

    Mukul