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TMS320C6416: AECLKOUT1/2 during nRESET is Low

Part Number: TMS320C6416


I have a question from my customer.

They are using AECLKIN, CLKIN, AECLKOUT1/2 as below configuration.
a) AECLKIN : 100MHz input
b) CLKIN : 50MHz synchronized with a) input
c) AECLKOUT1 : 100MHz synchronized with a) output
d) AECLKOUT2 : 50MHz synchronized with b) output

a) and b) are enabled as soon as system power-up.
nRESET is Low for 2 seconds after power-up then, goes to High.

While nRESET is Low for 2 seconds, c) and d) are enabled or not?

Thanks and regards,
Koichiro Tashiro

  • Hi Tashiro-san

    I will see if there is anyone internally available to discuss this query , as this is a very old design - I am not sure we will have any details beyond what you see on product folders. 

    What is the reason of the question? Is the customer seeing any issues? 



  • Hi Mukul,

    Here is the background of the question.
    There are FPGA and LAN-IC on the board and reset release sequence is;
    FPGA => LAN-IC => DSP
    As FPGA and LAN-IC require “synchronous reset”, so clock needs to be on when the reset is released.
    The clocks to FPGA and LAN-IC are provided from DSP AECLKOUT* and BECLKOUT*
    (in the previous post, I mention only AECLKOUT*, but both AECKLOUT* and BECLKOUT* are used in fact)

    According to datasheet (SPRS146N) Figure 37, it seems ECLKOUT1 goes to HiZ and ECLKOUT2 is on with 1/4 of ECLKIN.
    But it is not clearly mentioned ECLKOUT2 is on while reset is low.
    Could you confirm above points?

    Thanks and regards,
    Koichiro Tashiro

  • Hello Tashiro-san

    We cannot say it definitely. I do not have access to design, hardware or specifications. 

    From the user guide there’s a chance that it is clocking during reset, since the EN bits default to enabled in GBLCTL registers but EK2RATE defaults to /4 so it will be 25 MHz during or coming out of reset.

    I think customer will need to confirm behavior in their setup.