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AM3358-EP: Determine end of UART data TX

Part Number: AM3358-EP

We are developing an application on a custom board running an AM3358.  We're using sys/bios 6.75.2, am335x PDK 1.0.16 and CCS8.

We are sending 150 bytes via a UART using the sys/bios UART driver.  The UART is opened in callback mode.  However, we get the write callback when the last chunk of data is written to the FIFO, not when the TX is complete.  I need to know when the TX is complete.  Is there a way to configure the UART to notify the app when all the data has been sent?  If not, is there a way to poll the FIFO to determine when it's empty? 

  • Hello,

    Take a look at Table 19-11 in the AM335x TRM:

    Additionally look at the UART_TestExample in the pdk. Instructions on how to build that can be found here:

    Specifically, look at the UART_HWAttrs struct in UART_v1.h in the PDK.

    Take a look at the UART-socGetInitCfg and UART_socSetInitCfg functions as well



  • Hi Max,

    The information you provided is basic setup and use of the UART.  We already have it running and configured.  Table 19-11 shows the interrupts that are supported.  As you can see, RHR and THR are the only two that involve the buffering/sending of the data.  And when the FIFO is enabled, they both fire when the threshold is crossed.  Both these interrupts are handled by the driver.  The driver get's the interrupts and either reads or writes data to the FIFO (depending on TX or RX).  It's the driver that calls the write complete callback in the application, and it does this when the last chunk of data is written to the FIFO, not when the TX is complete.

    For simplicity sake, lets ignore the threshold levels for now.  The FIFO is 64 bytes.  The data is 150 bytes.  When the write begins, the driver writes the first 64 bytes to the FIFO and the UART starts sending the data out.  The driver will then get an interrupt when the UART needs more data in the FIFO.  The second 64 bytes are written to the FIFO. The UART writes the data out and sends the driver another interrupt.  The driver writes the last 22 bytes to the FIFO and immediately calls the write callback in the application.  So the app gets the write complete callback, but there are still 22 bytes in the FIFO being sent out.

    I don't believe the driver, or chip, provide an interrupt when the TX is complete when the FIFO is enabled.  So my question is, from our app how can I tell when all the data has been sent?

  • Hi Shawn,

    I'm looking into this and will try and have an answer to you by tomorrow.



  • Hi Max,

    It's been almost 2 weeks.  Any info on this?

    In the mean time I can tell you what I've tried.  According to the TRM (section, the LSR_UART register, field TXSRE is defined as follows:

    0h = Transmitter hold (TX FIFO) and shift registers are not empty.
    1h = Transmitter hold (TX FIFO) and shift registers are empty.

    I've implemented a timer that will fire just before the end of the TX.  I loop, checking this register field until it is 1.  

    When watching this on the scope, the register field goes to 1 anywhere from 7-14us before the data is finished sending on the wire.  So there is something between the FIIFO/shift register and the wire.  I need to know when the data TX is complete (on the wire).



  • Hi Shawn,

    Sorry for the delay,

    Have you looked into the UARTIsTransmitterEmpty function in <PDK_Install>\packages\ti\csl\uart.h?