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TMS320C5504: EMIF wait pin mapping

Koichiro Tashiro
Mastermind 21140 points
Part Number: TMS320C5504

Hi,

My customer has a question for C5504 EMIF EM_WAIT signals.

According to EMIF user’s guide (sprugu6b.pdf), Table 1-41, AWCCR2 register description,
EM_WAIT[3:0] pins can be mapped to CS[5:2].
https://www.ti.com/lit/ug/sprugu6b/sprugu6b.pdf

But datasheet sprs659g says actual pin names are EM_WAIT[5:2].
https://www.ti.com/lit/ds/symlink/tms320c5504.pdf

Customer wants to use EM_WAIT3 pin for CS3.
In this case, which one should be programmed in CS3_WAIT bit field in AWCCR2 ?
1h or 3h ?



Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru 50170 points

    Hi, Koichiro,

    I am checking it internally. Once I get the answer, I'll post it back here.

    Rex

  • 0
    TI__Mastermind 29180 points

    Hi Koichiro-san,

    I found out that the datasheet name changed from PG1.x to PG2.0.

    EM_WAIT0 -> EM_WAIT2
    EM_WAIT1 -> EM_WAIT3
    EM_WAIT2 -> EM_WAIT4
    EM_WAIT3 -> EM_WAIT5

    But it looks like this change was not carried into the EMIF User's Guide. We'll file a bug to track this issue.

    So the signals described in the EMIF User's Guide as EM_WAIT0, EM_WAIT1, EM_WAIT2, EM_WAIT3 are connected to the pins described in the TMS320C5504 datasheet as EM_WAIT2, EM_WAIT3, EM_WAIT4, EM_WAIT5, in that order.

    In that case AWCCR2 should be programmed so bit field [3-2] CS3_WAIT = 1h Use the EM_WAIT1 pin so that CS3 monitors the EM_WAIT3 pin. I believe CS3 could monitor any of the other wait pins: EM_WAIT2, 3, 4, or 5 by configuring this AWCCR2 register.

    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    TI__Mastermind 21140 points

    Hi Mark,

    Thanks for your clarification.

    Now customer configure AWCCR2.CS3_WAIT=1 to select EM_WAIT3, but it seems the wait signal does not working.
    Please see attached waveforms.
    EMIF_Wait.pptx
    Page#1 shows the case when EM_WAIT3 is active(H), but the access is completed.
    I checked register configurations and it seems they are correct (configurations in RED)

    Page#2 shows the case when RSTROBE is simply increased to 20h.
    It works properly.

    Page#3, EM_WAIT5 is selected in AWCCR2.CS3_WAIT.
    On customer’s board, EM_WAIT5 is not used and pull-up H.
    As you can see, it seems only write access is extended by EM_WAIT5 signal until it times out (MEWC=64).
    But EM_WAIT5 does not affect to read accesses.
    I do not see there is any configuration to enable/disable wait signal for read or write only.

    Why EMIF works such unexpected way?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 29180 points

    Hi Koichiro-san,

    Thank you. I understand the problem now.

    Very strange that the read does not extend the strobe cycle when either EM_WAIT3 or EM_WAIT5 is detected high. I think these register values look okay also.

    Can the customer read back the values written to the registers AWCCR1, AWCCR2, ACS3CR1, ACS3CR2? Do they read back values that match what was written? Some IP like SPI require upper and lower parts of the register (32-bit) to be written atomically.

    What are the voltages for DVDD_EMIF and the IO voltage of the EMIF device? What voltage is the EM_WAIT3 signal when driven high?

    During a WRITE access on CS3, does EM_WAIT3 get driven high to extend the write cycle? Is the wait pin working during writes?

    Can you also tell me what is the value of the NANDFCR register?

    Is there any way to test EM_WAIT4 during writes and reads?

    EDIT 1 - Are any interrupts bits set in  Interrupt Raw Register EIRR register?

    EDIT 2 - Does increasing the value of RSTROBE, say to 10 or 13 allow the WAIT signal to be detected and extend the cycle? The setup time can be 53ns from WAIT valid to OEn rise (without counting any wait states added).

    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    TI__Mastermind 21140 points

    Hi Mark,

    Here are some feedback from customer, but there are no suspicious points found.

    - When they read back the values of AWCCR1, AWCCR2, ACS3CR1 and ACS3CR2, all values are read as expected.
    See below memory window. These are for the case EM_WAIT5 is selected.


    - EIRR = 0x003D, so all WR[3:0] bits are set. And AT=1 (due to EM_WAIT5 timeout).

    - CVDD is 1.3V. DVDD_EMIF is 2.99V. EM_WAIT3 is 3.0V(High), EM_WAIT5 is 2.98V(Pull-up).

    - NANDFCR = 0x0000

    - Customer tried ACS3CR1=0x653D(RSTROBE=10), but it does not help.

    It is really strange.
    Could you try to check the EM_WAIT3 really works on EVM?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 29180 points

    Hi Koichiro-san,

    All 4 wait pins are accessible on the C5515 eZdsp and C5515 EVM boards. These devices are the same die as C5504.
    One could pull each EM_WAIT one high and observe with a scope to see if EMIF extends each EMIF read and write access to the timeout limit.
    The CSL examples or Spectrum Digital NOR flash example could be used as a starting point.

    Can you perform the experiment?

    Regards,
    Mark