Other Parts Discussed in Thread: AM5718
We are currently using in our design the AM5718 CPU to control an SPI NOR flash in Dual SPI mode with the highest frequency possible. Our SPI NOR flash support a maximum frequency of 133Mhz. According to the CPU datasheet (and previously verified by the TI support through ticket CS0294210), the minimum cycle time in SPI mode 0 is set to 11.71ns (85.4 Mhz). I would like to know how we could achieve the specified 85.4Mhz frequency with SPI Mode 0.
Using register CM_L4PER2_QSPI_CLKCTRL, I'm able to reach the 64MHz by using either the FUNC_128M_CLK (128Mhz) with a divisor of 2 or the PER_QSPI_CLK (192Mhz) with a divisor of 3 or 96Mhz using the PER_QSPI_CLK with a divisor of 2 (but 96MHz is already above the specified 85.4Mhz).
It looks like the FUNC_128M_CLK is fixed to 128Mhz, so is it possible to modify the PER_QSPI_CLK to produce 85.4Mhz ? According to the datasheet, there is a mention page 7515 that the PER_QSPI_CLK has a ROM-Code default value of 192Mhz, with a hint that this value can be modified through the CH (Configuration Header) section. However i don't see how we could reach 85.4Mhz this way either.
Many thanks for your help !