AM5718-HIREL: Maximum QSPI frequency

Hi Kamel,

I will check on this internally and get back to you in couple of days.

Best Regards,
Keerthy

Kamel Hacene14 said:

We are currently using in our design the AM5718 CPU to control an SPI NOR flash in Dual SPI mode with the highest frequency possible.

Why are you using Dual SPI mode rather than Quad SPI mode?  This seems like a bigger issue in my view.

Kamel Hacene14 said:

Using register CM_L4PER2_QSPI_CLKCTRL, I'm able to reach the 64MHz by using either the FUNC_128M_CLK (128Mhz) with a divisor of 2 or the PER_QSPI_CLK (192Mhz) with a divisor of 3 or 96Mhz using the PER_QSPI_CLK with a divisor of 2 (but 96MHz is already above the specified 85.4Mhz).

The PER_QSPI_CLK signal comes from DPLL_PER output H13.  If you're seeing PER_QSPI_CLK = 192 MHz, that corresponds to H13=4.  Changing H13 to 9 will result in PER_QSPI_CLK = 85.3 MHz.

Kamel Hacene14 said:

According to the datasheet, there is a mention page 7515 that the PER_QSPI_CLK has a ROM-Code default value of 192Mhz, with a hint that this value can be modified through the CH (Configuration Header) section.

Related to my initial question, if you could use the quad mode instead of the dual mode, the boot ROM can boot at 48 MHz (with 4 data pins) instead of 12 MHz using 1 data pin.  This would give you the best performance for loading your bootloader (u-boot-spl, etc.).  That would be much easier than trying to use the configuration header.  For subsequent items being booted, u-boot-spl can configure DPLL_PER the way you want it such that you can operate the QSPI at full speed.

Kamel Hacene14 said:

Ah yes i did not see the CM_DIV_H13_DPLL_PER register. Currently i cannot test this on our design board, but i made a few tests with an am5718 IDK board and was able to get the 85.3MHz. Thanks !

Great! I'm glad you were able to get that working.  There's one other thing that I want to note.  Using the QSPI in Mode 0 requires a Manual I/O Mode to be applied (i.e. related to the IOdelay module).  This is noted in the AM5718 Data Manual in "Table 7-2. Modes Summary".  It says that QSPI Mode 3 requires no virtual/manual modes, but Mode 0 requires that you apply the timings from QSPI1_MANUAL1 which is further described in "Table 7-47. Manual Functions Mapping for QSPI".  If you're using the pinmux tool (and you should!) to generate your pinmux settings, then all of this should be done for you.  If this is all new to you, please be sure to read the app note:

AM57xx Sitara™ IO Configuration Requirements
http://www.ti.com/lit/sprac44

Kamel Hacene14 said:

if you have the answer about the support of the DTR mode on the am5718 processor, i'd love to know,

I don't have specific experience using this mode.  However, the TRM indicates it is supported.  In section 24.5.1 "Quad Serial Peripheral Interface Overview" it specifies "dual read support".  Correspondingly the register QSPI_SPI_SETUP0_REG has a bitfield called READ_TYPE that can be set to 1 for dual read.

Brad Griffis said:

Kamel Hacene14

Ah yes i did not see the CM_DIV_H13_DPLL_PER register. Currently i cannot test this on our design board, but i made a few tests with an am5718 IDK board and was able to get the 85.3MHz. Thanks !

Great! I'm glad you were able to get that working.  There's one other thing that I want to note.  Using the QSPI in Mode 0 requires a Manual I/O Mode to be applied (i.e. related to the IOdelay module).  This is noted in the AM5718 Data Manual in "Table 7-2. Modes Summary".  It says that QSPI Mode 3 requires no virtual/manual modes, but Mode 0 requires that you apply the timings from QSPI1_MANUAL1 which is further described in "Table 7-47. Manual Functions Mapping for QSPI".  If you're using the pinmux tool (and you should!) to generate your pinmux settings, then all of this should be done for you.  If this is all new to you, please be sure to read the app note:

AM57xx Sitara™ IO Configuration Requirements
http://www.ti.com/lit/sprac44

Ah thanks for the tip ! I'm not personally familiar with the pinmux tool, our hardware team is usually in charge for this part and just provides us with the iodelays values. I'll forward the manuals to them !

Brad Griffis said:

Kamel Hacene14

if you have the answer about the support of the DTR mode on the am5718 processor, i'd love to know,

I don't have specific experience using this mode.  However, the TRM indicates it is supported.  In section 24.5.1 "Quad Serial Peripheral Interface Overview" it specifies "dual read support".  Correspondingly the register QSPI_SPI_SETUP0_REG has a bitfield called READ_TYPE that can be set to 1 for dual read.

Ah we're in fact using the dual read command to get two data signals at the same time from the nor flash (Dual SPI). The Dual Transfer Rate is another command (which i've never used neither) which transfer addresses and read data on both edges of the clock. So it is possible to combine Single/Dual/Quad SPI with DTR to reach some awesome performances without having to increase clock frequencies, which save some space on board schematics.

Have a nice day !

Kamel