[FAQ] DRA829V/TDA4VM: How can I check if cache is enabled or not for R5F

Hi Linda Xie,

If you check the R5F TRM (https://developer.arm.com/documentation/ddi0460/c/System-Control/Register-descriptions/c1--System-Control-Register?lang=en ) section 4.3.16 c1, System Control Register, you will see the following:

1. 12th Bit (I bit) determines if the I cache is enabled or not

2. 2nd Bit (C bit) determines if the D cache is enabled or not

This register can be read from CCS via the Register -> System registers -> CP15_SYSTEM_CONTROL register.

For you application, I see the value as 0x00E5187D - here both the I and the C bits are 1, hence we can confirm that the I cache and the D cache are both enabled.

On a side note, there is an implementation for the SYSBIOS code at bios_6_83_00_18\packages\ti\sysbios\family\arm\v7r\Cache_asm.sv7R - see ti_sysbios_family_arm_v7r_Cache_getEnabled__E , ti_sysbios_family_arm_v7r_Cache_enableL1d__I and ti_sysbios_family_arm_v7r_Cache_enableL1p__I functions.

The above mentioned functions also try to get the status of the I and D caches which in this case we are viewing from the CCS System Registers View.

Regards,

Karan