AM3352: AM3352BZCZ100 : datasheet vs Technical Reference Manual for ADC frequency

I can see where the 24MHz limit mentioned in the TRM and note associated with it is causing confusion.

The Touch Screen Controller / ADC has an internal clock divider which is configured in the ADC_CLKDIV register. The post divided clock frequency should be configured to operate in the range of 1 - 3 MHz.  A post divided ADC clock frequency of 3 MHz provides the maximum sample rate of 200 kSPS assuming you configure the ADC in continuous mode with OpenDelay and SampleDelay set to their default values. The ADC acquires the signal on the sampling capacitor for a minimum of two ADC clock cycles and the conversion always takes 13 ADC clock cycles.  So the fastest sample rate occurs every 15 ADC clock cycles.

It appears the TRM is trying to tell the user a 24 MHz is required to achieve the maximum sample rate of 200 kSPS . It is possible to apply a 25 MHz or 26 MHz clock to the ADC module since they are valid operating frequencies of the high frequency oscillator.  However, it is not possible to configure the post divider to value that provides a 3 MHz clock when using any of the other valid high frequency oscillator options.

Hopefully, this answers your question.

Regards,
Paul