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CCS/TMDSEVM6678: how to config to ipc + hyperlink setup?

Part Number: TMDSEVM6678

Tool/software: Code Composer Studio

hi~

i have 2 dsp (tmdsevm6678LE).

i was tested hyplnk_evmc6678_C66BiosExampleProject.

in example, .cinit is L2SRAM

it's OK. 

and, i was tested image_processing_evmc6678l example ( 8core ipc only test)

in example, .cinit is MSMCSRAM

it's also OK

between hyplnk example and ipc example, .cinit is diferent

so i tested hyplnk_evmc6678_C66BiosExampleProject with .cinit = "MSMCSRAM"

using core is only 0.

1. dsp1 and dsp2 run is ok

2. dsp1 and dsp2 run all cores. <<<<<<<<<<<<<< Fatal error detected

-----------------------------------------------------------------------------------------------------------------

void EVM_init(void)
{
platform_init_flags init_flags;
platform_init_config init_config;
uint32_t core;

if ( DNUM == 0u) {
platform_uart_init();
platform_uart_set_baudrate(115200);
(void)platform_write_configure(PLATFORM_WRITE_UART);

memset(&init_flags, 0x00, sizeof(platform_init_config));
memset(&init_config, 0x00, sizeof(platform_init_config));

if (platform_init(&init_flags, &init_config) !=Platform_EOK) {
platform_write("Platform failed to initialize, errno = 0x%x \n", platform_errno);
}

platform_write("Enable Master Core-%d\n",DNUM);
platform_write("hyplnk test with .cinit=MSMCSRAM\n");

#if 1
DEVICE_REG32_W(DSCR_KICK0, DSCR_KICK0_KEY);
DEVICE_REG32_W(DSCR_KICK1, DSCR_KICK1_KEY);

for( core = 1u; core < 8u; core++) {
DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)&_c_int00);
platform_delay(1u);
}

for( core = 1u; core < 8u; core++) {
DEVICE_REG32_W(IPCGR(core), 1);
platform_delay(1000);
}
#endif
}
}

-----------------------------------------------------------------------------------------------------------------

and then, hyperlink run only core0

-----------------------------------------------------------------------------------------------------------------

//int main(void)
Void hyplnk_main(UArg a0, UArg a1) // 20201113 thread...
{
hyplnkRet_e retVal;
uint32_t token;
uint32_t i;
int iteration = 0;
hyplnkExampleDataBuffer_t *dataBufPtr;
#ifndef __ARMv7
uint8_t mar;

#if 1 // 20201113 test by JC
if (CSL_chipReadDNUM() != 0)   <=== only run core 0
return;
#endif

TSCL = 1;
#endif

printf("[%s:%d] entry...(DNUM:%d)\n",__func__,__LINE__,DNUM); // 20201113 dbg by JC
#ifdef infraDMA
Qmss_Result localRegion,remoteRegion;
#endif

#if defined (SOC_C6678)
CSL_BootCfgUnlockKicker();
#endif

-----------------------------------------------------------------------------------------------------------------

Is it possible to use hyplnk only in a specific core?

What should I do to enable all the core and make hyplnk work?

my code is below...

jc_hyplnk_test2 (2).zip

  • in single core, DSP1 <-> DSP2 is OK

    but, in multicore, DSP1 <-- FATAL error detected --> DSP2...

    below is error logs.

    ------------------------------------------------------------

    [C66xx_0] About to do system setup (PLL, PSC, and DDR)
    Power domain is already enabled. You probably re-ran without device reset (which is OK)
    Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
    system setup worked
    About to set up HyperLink Peripheral
    ============================Hyperlink Testing Port 0
    ========================================== begin registers before initialization ===========
    Revision register contents:
    Raw = 0x4e901900
    Status register contents:
    Raw = 0x00000004
    Link status register contents:
    Raw = 0x00000000
    Control register contents:
    Raw = 0x00000000
    Control register contents:
    Raw = 0x00000000
    ============== end registers before initialization ===========
    Waiting for other side to come up ( 0)
    SERDES_STS (32 bits) contents: 0x03078d1b; lock = 1
    Waiting for other side to come up ( 1)
    ============== begin registers after initialization ===========
    Status register contents:
    Raw = 0x04402005
    Link status register contents:
    Raw = 0xccf00000
    Control register contents:
    Raw = 0x00006204
    ============== end registers after initialization ===========
    Waiting 5 seconds to check link stability
    Analyzing the connection for each lane
    Precursors 1 Analysis: 0,1,0,1,0,1,0,1
    Postcursors: 19 Analysis: 1,0,1,0,1,0,0,1
    Link seems stable
    About to try to read remote registers
    ============== begin REMOTE registers after initialization ===========
    Status register contents:
    Raw = 0x0440200b
    Link status register contents:
    Raw = 0xfdf0bdf0
    Control register contents:
    Raw = 0x00006204
    ============== end REMOTE registers after initialization ===========
    Peripheral setup worked
    [hyplnk_main:735] entry...(DNUM:0)
    Version #: 0x02010008; string HYPLNK LLD Revision: 02.01.00.08:Oct 26 2020:13:53:37
    About to read/write once
    About to read/write once
    Fatal error detected      <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< FATAL ERR
    Local fatal isr status.lError = 1
    Local fatal isr status.rError = 1
    Local fatal isr ECCErrors.dblErrDet = 1

    ------------------------------------------------------------

  • m trying to comunication test EVM1(C6678) <-> EVM2 (C6678) with hyplnk_evmc6678_C66BiosExampleProject.

    i run hyplnk_evmc6678_C66BiosExampleProject. in EVM1 and EVM2.

    Basically, when running the example using only core0 on both EVMs, it worked fine without any problems.

    Because all 16 cores ( 2 EVM ) must be used in my project, i modified  hyplnk_evmc6678_C66BiosExampleProject.

      1. .cinit : in cofiguration file, L2SRAM -> MSMCSRAM

      2. To run only when DNUM is 0, added main.c ( in EVM_init(), enable all cores) and modified main() -> hyplnk_main() thread in hyplnk_evmc6678_C66BiosExampeProject 

    but, this test was generated "Fatal error detected"...

    above test was EVM1[8core up] <-> EVM2[8core up] case....

    so. i was another case (EVM1[core0 only up] <-> EVM2[8core up] )  test.

    this case test is OK . 

    "Fatal error detected" occurs during hyperlink test only when both EVM1 and EVM2 cores are used.
    It was based on the basic example, but I do not know which part to modify, so I contact you...

    I can't understand why the things I set up to use all cores are a problem.

    Is there an error due to master/slave configuration when using hyperlink? ( example is hyperlink master mode. is it correct?)

    If the master/slave configuration is the cause, I wonder how to set one EVM to slave mode.

    Attach the modified code.

    1. core0 only  :

    jc_hyplnk_test_base.zip

    2. 8 cores up :

    jc_hyplnk_test_base_mult.zip