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OMAP-L138 McASP AHCLKR to ACLKR phase timing?

Judson Wilson
Intellectual 620 points
Other Parts Discussed in Thread: ADS1178

Hello, I am trying to find out a timing spec for the relationship between AHCLKR and ACLKR.  AHCLKR will be input from an external source, then divided down (possibly by a factor of 1) inside the OMAP, and output on the ACLKR pin.  This will be connected to an ADS1178 ADC, which mandates that the falling edges of it's master clock and serial clock must match within a quarter cycle of the master clock.  I cannot find any spec in the L138 datasheet.

Thanks,

- Judson

  • 0
    TI__Genius 14545 points

    Judson,

    Typically the master clock frequency (AHCLKX/R) for a CODEC is much faster than the serial clock (ACLKX/R), so i'm a bit inquisitive of why you would want to source AHCLKX/R and ACLKX/R at the same frequency?

    If ACLKX/R is divided down internally from AHCLKX/R, the phase alignment should only be delayed by propagation through the internal clock dividers, mux's and pin buffers. 

    I took a look at the ADS1178 and found the spec for the clock alignment, and it basically specs the jitter between the master clock and the serial clock can be between -1/4 and + 1/4 of the master frequency clock, which puts jitter at ~20nsec total.

    The minimum period of the master clock frequency is 37ns for the ADS1178, which correlates to a Maximum Input frequency is at 27.027 MHz.. Typically audio clocks around this frequency are 24.576MHz. Which provides a period of ~40ns. 1/4 of this would be 10ns, which would be the worst case scenario, and assumes that there is no jitter on the master clock as well. In reality, there will be some sort of jitter on every clock.

    10nS shouldn't be an issue for McASP AHCLK-to-ACLK edge phase specs.

    Are you measuring violations in your circuit?

     

     

     

     

     

     

     

  • 0 in reply to dabuan
    Intellectual 620 points

    Drew Abuan said:
    Typically the master clock frequency (AHCLKX/R) for a CODEC is much faster than the serial clock (ACLKX/R), so i'm a bit inquisitive of why you would want to source AHCLKX/R and ACLKX/R at the same frequency?

    Well we need to get 16 bits * 8 channels out of the ADC for every data sample.  That means that we need the serial clock to be at least 128 times the sample rate.   The slower option of the "fast" data rate for this ADC lists Fclk/Fdata at 256 - that would be a clock scale of 1/2 .   *Shrug*   There are at least 3 rates to keep track of and I keep getting confused.

    Drew Abuan said:
    Are you measuring violations in your circuit?

    Circuit isn't built yet, just trying to make sure everything works on paper before we spend money on boards.