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TMS320C6670: Restart of PCIe link

Part Number: TMS320C6670
Other Parts Discussed in Thread: SYSBIOS

Hello,

As an extension of the referred thread, may I ask to clarify the following.

Is there a way to restart PCIe link? We have certain scenarios, where DSP application remains running, but FPGA, which is PCIe End Point, is required to be reloaded with different firmware and restarted. We tried PCIESS power domain down, then up, re-initialization, noting seems to do the job.

Could you please clarify, whether this kind of use is possible with Keystone I, C6670? Is that possible with Keystone II, like K2G, K2H?

Thank you.

  • Hello,

    I will try and get an answer for your regarding this follow up question but please expect a bit of a delay due to New Years holiday.

  • Hi rrlagic 

    Ralph pointed me to this post. Let me discuss this internally further and will try to to get back to you soon.

    Regards

    Mukul 

  • Hi rrlagic

    Sorry I missed the subtle detail in your post/use-case scenario. 
    In the original post from the other customer, they are using C667x in EP mode. 

    In your  follow-up question case on this post, it looks like PCIESS is RC and FPGA is EP.  In this case, I am not aware of any limitations on  PCIESS supports issuing of hot reset to endpoints.  

    What is your software driver base etc ( I do not know what we support in the SDK PCIe driver etc)? Feels like you have used TI Keystone products for a while, so is this a new requirement or something that recently is not working?

    When you ask about K2G and K2H, have you used Linux side PCIe drivers etc and seeing any issues or is that purely a question out of curiosity and the issue pertains to c6670 only and you want to understand what is it for the rest of the KS device family?

    Regards

    Mukul 

  • Hi Mukul,

    Yes, we run RC on C6670 and EP on FPGA.

    To my understanding, hot reset is what can be used to bring device receiving it to its initial condition without power cycling or firmware reload. We want something beyond it. So my question is not that much related with hot reset itself, but rather possibility to re-establish the link.

    We run SYSBIOS application on C6670. First steps like power domain enable, link training enable are borrowed from MCSDK examples, rest like translation, MSI - in house code.

    The system under consideration is in use already. We want to be able to quickly re-establish the link after FPGA reload. We did some experiments, but neither succeeded. So as a workaround we reboot DSP too. In worst case BOOTP frame for Ethernet boot may come as late as in 3 seconds, application download and startup adds about 1.5 seconds, while FPGA reboot takes no more that 100 milliseconds. We need this switching to occur pretty often, so having those delays makes our system not very well suited for that for such scenario. That's why I'd like to know whether that is possible in principle.

    As to K2G, K2H, we are planning 2 more designs with mentioned SoCs, and requirement to quickly reboot FPGA and re-establish PCIe will be there too. So I am curious, if we could relieve our problem with those SoCs. Colleague of mine is doing his steps with K2G, we looking for opportunity to purchase K2H. Either way, Linux on SoC will not be granted access to PCIe, we reserve it solely for communication of DSP with FPGA.

    Thanks.