66AK2H06: DDR3 configuration questions

Hello Tashiro-san

Regret the late response on this 

For Q1: The DDR programming including programming the DDR controller and PHY: The SDTIMx is a register in the EMIF/DDR controller register for DRAM timing.  DTPR is the PHY register for DRAM timing.  PHY does not perform DRAM reads/writes, so most of them are unused, however, it uses some of these for leveling and other functions, so recommendation is to program them both controller and PHY timings to correct required values per DRAM datasheet.  This is as per the recommendations the the DDR initialization application note (SPRABX7)

For Q2: Please follow the gel file and the DDR initialization application note. I believe Tom had confirmed in some other threads that the User Guide has some typos and CKE 500 uS is not needed for KS2 family (it was needed for KS1 family). User guide needs to be corrected. 

e2e.ti.com/.../3308262

For Q3: FRQSEL needs to program it to the correct value based the PLL reference clock freq supplied to the PHY not the DRAM clock freq.  PLL reference clock = DRAM clock / 2 or DDR data rate / 4.  For 1333 data rate, DDR clock will be 667 MHz and PLL reference clock will be 333 MHz, so need to program 01.  I do not have the background on why it is programmed to 11. 

For Q4: CPPC in PLLCR stands for “Charge Pump Proportional Current Control”.  This is for PLL charge pump.  The value used might comes from the PHY specification.  Please use the recommended value. 

Hope this helps.

Regards

Mukul 

Hi Mukul,

Thanks for your reply.
Customer understood Q1 and Q2.

For Q3 and Q4, customer found Errata description about FRQSEL and CPPC.
Please refer to KeyStoneII.BTS_errata_advisory.35 in SPRZ402F.
According to this document,
FRQSEL=0x3 and CPPC=0xF for both DDR3-1600 and DDR3-1333.
These values are valid for silicon revision 3.1, right?

Thanks and regards,
Koichiro Tashiro

Tashiro-san

KeyStoneII.BTS_errata_advisory.35 and 34 do not apply to rev 3.1 silicon - these issues were fixed, so my recommendation will be to use the values that you get from the DDR3 initialization guide and DDR3 user guide , excel spreadsheet etc. 

Regards

Mukul 

Hi Mukul,

There is discrepancy between DDR3 user’s guide and spreadsheet for DDR3_PTR0 register tPHYRST recommendation.
User’s guide (SPRUHN7C) p96 says “TI recommends setting this to 15.”
But spreadsheet value is 16(0x10). GEL also uses 16(0x10)

0x10 is correct value?

Thanks and regards,
Koichiro Tashiro