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TDA4VM: The question regarding to J721E board I2C isolation design

Part Number: TDA4VM
Other Parts Discussed in Thread: SN74LVC2G66,

Hi Expert,

 In TDA4VM schematic doc, there is a voltage isolation SN74LVC2G66 to isolate I2C input (SOC_WKUP_I2C0_SDA)and output (WKUP_I2C0_SDA), the design purpose is to isolate and protect singal from different power domain (VSYS_MCUIO_3V3 and VSYS_IO_3V3), right?

 But according to SoM I2C TREE DIAGRAM in page5 in schematic pdf, for other I2C signal which input and output are also from different power domain,  there is no voltage isolation existed, please clarify why only SOC_WKUP_I2C0_SCL/SDA use a voltage isolation . this is for a customized HW design question.


  • The above circuit is to support I2C isolation between different power modes.  The WKUP_I2C0 connects to PMIC, which is on the MCU_IO power domain as well as EEPROMs that are on the MAIN_IO power domain.  The EVM support a low power mode (MCU_ONLY) in which the MCU power domain stays active but the MAIN power domain is OFF (including the EEPROMs).  In this mode, we needed WKUP_I2C0 to remain active (for PMIC communication) but needed to isolate the bus form the un-powered EEPROMs.  Because the bus has peripherals that spanned both power domains - isolation was required.