Hello Champs,
Customer failed to initialize SRIO when connecting c6671 to FPGA, PORT_OK is always 0.
1. C6678+FPGA SRIO can connected successfully.
2. C6671 SRIO loopback is OK and FPGA SRIO loopback is OK.
3. POR#、RESETFULL#、RESET# is pulled high by FPGA, the sequence is RESET->POR#->RESETFULL#. NMI#、LRESET#、LRESETNMIEN#、CORESEL[0：3]、HOUT are just connected to FPGA without configuration.
4. configure 1x, 2.5G, the clock chip is CDCM61002, DSP clock is 250MHz, FPGA clock is 125MHz, but both are configured to 2.5GHz.
5. FPGA load the code first, then dsp load the code.
Thanks.
Rgds
Shine
