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DRA718: DDR3 alternatives and questions about it

Jens G
Intellectual 2555 points
Part Number: DRA718
Other Parts Discussed in Thread: TIDEP-0097,

Dear TI Team, 

please could you take a look into the customer question below. 

  1. Part number used in TIDEP-0097 : MT41K512M16HA-125 AIT:A : SDRAM - DDR3L Memory IC 8Gb (512M x 16) Parallel 800MHz 13.5ns 96-FBGA (14x9) 

  1. Alternate Part number used at customer project : MT41K512M16VRP-107 IT:P  : DRAM Chip DDR3L SDRAM 8Gbit 512Mx16 1.35V 96-Pin TFBGA; DDR3 memory suggested by Distribution.

 DS: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/ddr3l_8gb_x16_1cs_twindie_v00h.pdf?rev=22af12ce29de4defa41e06e9beebd61f

I ask you to clarify on our below mentioned questions;

  1. Does this alternate DDR3L MT41K512M16VRP-107 IT:P   suitable to DRA718BJGCBDRQ1 with existing SDK support or we need to do some modifications on SW?
  2. If we need to do some modification in existing SDK TI SW, does TI supports for the same ?, and what types of modifications are required in SDK?, Need clarifications for the same.
  3. Does DRA718BJGCBDRQ1 support Twin Die DDR3L memory or not?
  4. Does DRA718BJGCBDRQ1 support 1.07ns@CL=13 (DDR3-1866) or not?
  5. Routing guidelines for the DDR3 signals in order to decrease the latency with the mentioned DDR3 memory Part No. MT41K512M16VRP-107 IT:P .
  6. is there any other guideline need to follow during PCB layout for smooth integration of new DDR3L memory?

Thanks and best regards

Jens

  • 0
    TI__Mastermind 26655 points

    Hi,

    Please refer to this post where several of the same questions (exact same memory part #s) were asked: e2e.ti.com/.../3602765

    1) IO settings (such as drive / ODT) may need to change, but addressing should not change (a 4Gb 8-bit DDR3 memory has the same number of banks / columns / rows as a 8Gb 16-bit memory).

    2) Outside of potential IO register settings, I am not aware of any other required SW modification. TI offers an XLS tool to adjust IO settings.

    3) See E2E post mentioned above, same rules apply for DRA718.

    4) A CAS latency of 13 is not supported, but this setting should only be used at much faster frequencies than supported by the DRA71x part. The memory should be backwards compatible with slower frequencies, where a slower CAS latency can be used. Please confirm with memory vendor.

    5) I apologize but I do not understand what is being asked. Can you please clarify?

    6) Please see DRA718 datasheet for layout / routing guidelines. 

    Best regards,
    Kevin