Hi,
The customer experienced a memory timing problem while using TMS320C6713B.
Accessing FPGA (DPRAM) to Async. via EMIF Interface.
Data0 (ED0) changes were measured before the Write Enable signal (AWE) became Deasserting when DSP was writing.
I would like to ask if there is any way to configure to meet the Spec. required by DSP Datasheet.
