Hi,
We have a SBL that is stored in NOR memory and it is working fine. The size of the SBL is around 210kB. When debugging another problem I tried increasing the size of the SBL by adding some dummy data so the binary goes beyond 256kB. As soon as I go above this the execution stops when configuring the AMMU. No problem as long as the size of the SBL is below 256kB.
The actual call that is causing the problem is this. Any suggestions why the size increase of the SBL causes this error? According to the documentation the image size can be up to 504kB.
/* Medium Page Translations * Pages mapped by RBL 0th page: P.A. 0x40300000 to V.A. 0x00300000 * SBL re-maps 1st medium page, so clear 1st page mapping by RBL */ pageConfig.ammuPageType = AMMU_PAGE_TYPE_MEDIUM; pageConfig.ammuPageNum = 1U; pageConfig.policyRegVal = 0U; pageConfig.physicalAddress = 0U; pageConfig.logicalAddress = 0U; AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
This code is taken from tda3xx/src/sbl/ti/boot/sbl_auto/sbl_utils/src/tda3xx/sbl_utils_tda3xx.c and the function is void SBLUtilsConfigIPU1DefaultAMMU(void)
Extra information. We are running on a XTDA3SXXBDABFQ1 and the linker file looks like this.
/** * \file lnk_tda3xx_m4_nor.cmd * * \brief This file contains the System Memory Map used by Secondary * Bootloader (SBL) for NOR boot mode for tda3xx SoC. * * \copyright Copyright (C) 2014 Texas Instruments Incorporated - * http://www.ti.com/ */ -stack 0x1000 /* SOFTWARE STACK SIZE */ -heap 0x1000 /* HEAP AREA SIZE */ /* SPECIFY THE SYSTEM MEMORY MAP */ MEMORY { IRAM_MEM: org = 0x00000000 len = 0x4000 /* IRAM */ OCMCRAM1_0: org = 0x00300000 len = 0x00000100 /* OCMC RAM mapped to 0x40300000 */ OCMCRAM1_1: org = 0x00300100 len = 0x00000100 /* OCMC RAM mapped to 0x40300100 */ OCMCRAM1_2: org = 0x40300200 len = 0x00000100 /* OCMC RAM */ OCMCRAM1_4: org = 0x40300300 len = 0x00000100 /* OCMC RAM */ OCMCRAM1_3: org = 0x00300400 len = 0x0007FC00 /* OCMC RAM mapped to 0x40300300 */ NOR_0: org = 0x08000000 len = 0x00000200 /* NOR Memory Region1 - NOR Init Code */ NOR_1: org = 0x08000200 len = 0x00000100 /* NOR Memory Region2 - IPU Core1 Init */ NOR_2: org = 0x08000300 len = 0x03FFFD00 /* NOR Memory Region3 - Common */ } /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { .intvecs : load > NOR_2 .intc_text : load > NOR_2 .sbl_init : load > NOR_0 .ipu1_1_init : load > NOR_1 .init : load > NOR_2 .text : load > NOR_2 /* CODE */ .data : load = NOR_2, run = OCMCRAM1_3 LOAD_START(dataLoadStart) LOAD_END(dataLoadEnd) RUN_START(dataRunStart) .const : load > NOR_2 /* GLOBAL CONSTANTS */ .cinit : load > NOR_2 .bss : load > OCMCRAM1_3 /* UNINITIALIZED OR ZERO INITIALIZED */ /* GLOBAL & STATIC VARIABLES */ RUN_START(bssStart) RUN_END(bssEnd) .stack : load > OCMCRAM1_3 /* SOFTWARE SYSTEM STACK */ RUN_START(stackStart) RUN_END(stackEnd) .plt : load > NOR_2 .sysmem : load > NOR_2 .img_hdr : load > OCMCRAM1_2 .img_hdr1 : load > OCMCRAM1_4 .tesoc_img : load > OCMCRAM1_3 }
The whole function that causes the crash. If the faulty call is commented out there are other calls after that one that causes the error as well.
void SBLUtilsConfigIPU1DefaultAMMU(void)
{
ammuPageConfig_t pageConfig = {0U};
uint32_t index;
/* Large Page Translations
* Pages mapped by RBL: 0th page: P.A. 0x08000000 to V.A. 0x08000000
* SBL re-maps remaining large pages, so clear page mappings by RBL
*/
pageConfig.ammuPageType = AMMU_PAGE_TYPE_LARGE;
pageConfig.policyRegVal = 0U;
pageConfig.physicalAddress = 0U;
pageConfig.logicalAddress = 0U;
for (index = 1U; index < AMMU_NUM_LARGE_PAGES; index++)
{
pageConfig.ammuPageNum = index;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
}
/* 1st large page mapping: P.A. 0x40000000U V.A 0x40000000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_LARGE;
pageConfig.ammuPageNum = 1U;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE1_POLICY;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE1_PHY_ADDR;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE1_VIRTUAL_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 2nd large page mapping: P.A. 0x80000000U V.A 0x80000000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_LARGE;
pageConfig.ammuPageNum = 2U;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE2_POLICY;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE2_PHY_ADDR;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE2_VIRTUAL_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 3rd large page mapping: P.A. 0x80000000U V.A 0xA0000000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_LARGE;
pageConfig.ammuPageNum = 3U;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE3_POLICY;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE3_PHY_ADDR;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_LARGE_PAGE3_VIRTUAL_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* Medium Page Translations
* Pages mapped by RBL 0th page: P.A. 0x40300000 to V.A. 0x00300000
* SBL re-maps 1st medium page, so clear 1st page mapping by RBL
*/
pageConfig.ammuPageType = AMMU_PAGE_TYPE_MEDIUM;
pageConfig.ammuPageNum = 1U;
pageConfig.policyRegVal = 0U;
pageConfig.physicalAddress = 0U;
pageConfig.logicalAddress = 0U;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 1st medium page mapping: P.A. 0x55020000U V.A 0x00000000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_MEDIUM;
pageConfig.ammuPageNum = 1U;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_MED_PAGE1_POLICY;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_MED_PAGE1_PHY_ADDR;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_MED_PAGE1_VIRTUAL_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* Small Page Translations
* Pages mapped by design 1st page: P.A. 0x55080000 to V.A. 0x40000000
* Change policy of this page for mapping 16 KB instead of 4 KB
* SBL re-maps IPU RAM in 1st medium page. Clear ROM and RAM mappings done
* by RBL
*/
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = 0U;
pageConfig.physicalAddress = 0U;
pageConfig.logicalAddress = 0U;
for (index = 0U; index < AMMU_NUM_SMALL_PAGES; index++)
{
if (1U != index)
{
pageConfig.ammuPageNum = index;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
}
}
/* 0th small page mapping: P.A. 0x43300000U V.A. 0x63300000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE0_POLICY;
pageConfig.ammuPageNum = 0;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE0_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE0_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 1st small page mapping: P.A. 0x55080000U V.A. 0x40000000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE1_POLICY;
pageConfig.ammuPageNum = 1;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE1_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE1_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 2nd small page mapping: P.A. 0x43304000U V.A. 0x63304000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE2_POLICY;
pageConfig.ammuPageNum = 2;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE2_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE2_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 3rd small page mapping: P.A. 0x42081000U V.A. 0x62081000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE3_POLICY;
pageConfig.ammuPageNum = 3;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE3_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE3_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 4th small page mapping: P.A. 0x4208B000U V.A. 0x6208B000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE4_POLICY;
pageConfig.ammuPageNum = 4;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE4_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE4_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 5th small page mapping: P.A. 0x4208C000U V.A. 0x6208C000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE5_POLICY;
pageConfig.ammuPageNum = 5;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE5_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE5_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 6th small page mapping: P.A. 0x4883A000U V.A. 0x6883A000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE6_POLICY;
pageConfig.ammuPageNum = 6;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE6_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE6_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 7th small page mapping: P.A. 0x420A0000U V.A. 0x620A0000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE7_POLICY;
pageConfig.ammuPageNum = 7;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE7_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE7_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
/* 8th small page mapping: P.A. 0x42086000U V.A. 0x62086000U */
pageConfig.ammuPageType = AMMU_PAGE_TYPE_SMALL;
pageConfig.policyRegVal = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE8_POLICY;
pageConfig.ammuPageNum = 8;
pageConfig.logicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE8_VIRTUAL_ADDR;
pageConfig.physicalAddress = SBL_UTILS_TDA3XX_AMMU_SMALL_PAGE8_PHY_ADDR;
AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);
}
