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TMS320C6742: Crystal Oscillator Design

Genius 3115 points
Part Number: TMS320C6742

Hi experts,

Please let me check "6.5 Crystal Oscillator or External Clock Input" in the datasheet(SPRS587F).

Q1: Regarding the connection circuit of the external crystal unit, is it correct that the capacitance of the load capacitors C1 and C2 should be selected between 10 and 20 pF each?

Q2:Is there any particular regulation for the load capacitance of the crystal unit?

Q3: Is the excitation level specified on the device side?
As far as I can tell from the data sheet, there is no problem as long as the equivalent series resistance is within the recommended value.

The customer is currently using the C6742 to start the design. I checked "OMAP-L13x / C674x / AM1x schematic review guidelines(SPRACK9)", but it was difficult to understand the clear regulation, so I would appreciate it if you could let me check.

Best regards,
O.H

  • Let me see what I can find on this for you. 

    --Paul

  • Hi Paul,

    Thank you for your reply.

    Could you please tell me what the current situation is?
    The customer is looking for an answer, so we would appreciate it if you could tell us the situation.

    Best regards,
    O.H

  • I was out last week and it looks like the person I was seeing input from did not get the notification. I have resent the notification.

  • The TMS320C6742 oscillator was only designed to operate with a load capacitance in the range of 10pf to 20pf and is expected to operate properly when the capacitive load is within the range. Crystals are cut to be resonate at their specified frequencies when loaded with a specific capacitive load. Therefore, the crystal selected should have a specified load capacitance that falls with the range of 10pf to 20pf. Once you select a crystal, the load capacitance implemented with C1 and C2 plus any PCB parasitic capacitance must match the value defined by the crystal. The capacitive load seen by the crystal is the series combination of C1 and C2 and the parallel capacitance of the PCB signal traces. In some cases, the PCB signal traces may add 2pf or 3pf of parasitic capacitance that is effectively in parallel with C1 and C2. For example, lets assume the crystal selected requires a 12pf load and each signal trace has about 2pF of capacitance.  In this case, the value of C1 and C2 plus any PCB parasitic would need to be 24pf without considering PCB capacitance. Since the PCB capacitance is 2pf you would subtract that from 24pF and the capacitor values required for C1 and C2 would be 22pf.

    It is important to get the load capacitance as close as possible to the value specified for the crystal. The resonant frequency of the crystal will shift from the expected resonate frequency when the load capacitance does not match specified load capacitance.

    The power dissipated in the crystal is defined by the following formula, where actual values of the ESR, ƒxtal, and CL should be used to yield a typical crystal power dissipation value. Using the maximum values specified for ESR, ƒxtal, and CL parameters yields a maximum power dissipation value.

    Pxtal = 0.5 ESR (2 π ƒxtal CL (VDDS_OSC))2

    The customer should read Usage Note 2.1.1 in the TMS320C6742 Silicon Errata if they are planning to use the internal oscillator with a external crystal circuit. Several customers have experienced noise immunity issues when using the external crystal circuit option. 

    If they decided to use this option, I would also recommend providing a zero ohm resistor option that can be installed later if need to connect the crystal circuit ground directly to the PCB digital ground in addition to the OSCVSS connection.

    Regards,
    Paul