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TMS320C6652: About the power supply sequence and the number of layers on the board

O.H
Genius 5350 points
Part Number: TMS320C6652
Other Parts Discussed in Thread: TMDSEVM6657, TIDEP0036, TMS320C6657

Hi experts,

My customer is using TMS320C6652 for their design and they are comparing it with TMDSEVM6657 as they go along. Please let me know about the following questions.

(1) Regarding the number of board layers, is it correct to assume that 6 layers will not be a problem?
"6.3.1.2 Stack Up - SDRAMs" in "DDR3 Design Requirements for KeyStone Devices (Rev. C)" recommends a minimum of 8 layers if the board area is large. The TMDSEVM6657 schematic has 12 layers, but they don't think it's necessary for this board (C6652 board) (based on the customer's circuit size).

(2) Regarding the control sequence of the power input and reset signal at startup, is it correct to assume that the parts that do not have a time specification are fine as long as the order is followed?
There are many parts in the datasheet "6.3.1 Power-Supply Sequencing" that do not have a time limit. For example, CVDD1 is described as "at the same time or shortly following CVDD", but we could not determine how much time it should be.

(3) After the input of CVDD and CVDD1, there is a period of tens of seconds when the clock input is not stable before the input of CVDD18. Can I assume that this is not a problem?
According to "6.3.1.1 Core-Before-IO Power Sequencing", there is no problem even if the clock is unstable during the period between CVDD1 and CVDD18 inputs or during the "Power Stabilization Phase". I would like to confirm this just in case. If there is a problem, it would be helpful if you could tell me what kind of processing is needed on the clock input pins.

Best regards,
O.H

  • +1
    TI__Guru* 78415 points

    Hi O.H

    Customer would need to follow/adhere to all the requirements listed in the application note. I am not aware of a 6 layer reference design, so they will need to be confident in their ability to follow the rules and guidelines to ensure compliance to recommendations. TI also does not do any layout reviews for these devices. 

    On power supply requirements recommend to follow the datasheet and the EVM where possible.

    On Q2 i see the following note too

    TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp

  • 0
    Prodigy 220 points

    O.H.

    (1)  Routing DDR3 in 6 layers will be challenging.  There is a trade-off between layers versus board space.  If you plan to only use 6 layers, the DDR routing section will require more space.  There are trace spacing rules and impedance control rules that must be met.  You will need to have solid reference planes adjacent to the DDR routing layers and you cannot route DDR tracks on adjacent layers due to broad-side coupling.

    (2) Proper power sequencing is required.  When applying the phrase  "CVDD1 at the same time or shortly following CVDD", you must verify that the CVDD1 voltage never exceeds the CVDD voltage.  This includes both when ramping and when discharging.

    (3) As Mukul said, "TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp".  Therefore, you cannot have 10s of seconds between power rails ramping.  Power, clock, and reset sequencing must follow the guidance shown in the Data Manual.

    Tom

  • 0 in reply to Thomas Johnson2
    Genius 5350 points

    Hi Mukul-san, Tom-san,

    Thank you for your reply.

    O.H said:
    (3) After the input of CVDD and CVDD1, there is a period of tens of seconds when the clock input is not stable before the input of CVDD18. Can I assume that this is not a problem?

    Sorry. There was a mistake in the description of (3).
    Wrong: "period of tens of seconds".
    Correction: "period of tens of milliseconds".

    I missed the NOTE in the datasheet, so I understand about (2) and (3).

    As for (1), we will proceed to follow the guideline document.

    Thanks for your support.

    Best regards,
    O.H

  • 0 in reply to O.H
    Genius 5350 points

    Hi Mukul-san, Tom-san,

    Sorry for the additional questions. Please let me confirm the following information.

    (4): If you have a reference design for the layer structure and pattern routing when using 3 units of DDR3 in 8 layers, could you please share it?

    (5): Is it correct that I can refer to the reference design for the layer structure and pattern routing of TMDSEVM6657 from the following website?
    >TIDEP0036:https://www.ti.com/tool/TIDEP0036

    (6): if you have the IBIS model of TMS320C6657 (or C6652), could you please share it?

    The customer is planning to use 3 units of DDR3.  Two of them are for data and one is for ECC, and they are referring to TMDSEVM6657 for the schematic. Basically, we asked them to follow the requirements in the application note, but they said it would be helpful to have design information on pattern routing around the DDR3 and clock, and PCB board layer structure. We would be grateful if you could provide us with some documents that would be useful for our customers.

    Best regards,
    O.H

  • 0
    Prodigy 220 points

    O.H.,

    (4) There is no other sample design available other than the C6657 EVM.

    (5) The full set of design files for the C6657 EVM is on the EVM manufacturer's website at  https://www.einfochips.com/partnerships-and-alliances/device-partnerships/texas-instruments/tms320c6657-evm/.  The TIDEP0036 design is an example for CODEC integration that only contains a subset of the EVM design files.

     (6) IBIS models are available on the product page at https://www.ti.com/product/TMS320C6657#design-development##design-tools-simulation.  Note that these IBIS models are for signal integrity simulation.  They do not include timing information.  Please see the KeyStone I DDR3 interface bring-up Application Report (SPRACL8) at https://www.ti.com/lit/an/spracl8/spracl8.pdf for more explanation.  It summarizes the design steps needed to layout and commission a DDR interface for the C665x devices.

    Tom

  • 0 in reply to Thomas Johnson2
    Genius 5350 points

    Hi Tom-san,

    Thank you for sharing the correct design information and the IBIS model of C6657.

    I researched carefully again and found the following thread. As stated here, we would like to tell our customers to refer to the C6654 IBIS model for the C6652 IBIS model.

    https://e2e.ti.com/support/processors/f/processors-forum/771252/tms320c6652-where-can-i-get-c6652-ibis-model

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru* 78415 points

    Hello 

    Yes you can point them to the C6654 IBIS models, however for the DDR topic, please keep in mind what Tom shared in his previous post

    Note that these IBIS models are for signal integrity simulation.  They do not include timing information.  Please see the KeyStone I DDR3 interface bring-up Application Report (SPRACL8) at https://www.ti.com/lit/an/spracl8/spracl8.pdf for more explanation.  It summarizes the design steps needed to layout and commission a DDR interface for the C665x devices.