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TDA4VM: GPIO Maximum Output Frequency in Linux and SysBios?

Part Number: TDA4VM
Other Parts Discussed in Thread: SYSBIOS

Hi TI,

I am currently testing the mimum delay I can get using GPIOs (in specific WKUP_GPIO0_6, which is connected to TP45) on TDA4VM. I did that for

  • Linux (using the gpio consumer interface in a kernel module (PSDKL V07.02.00.07))
  • SysBios (using the led_blink example from the pdk (PSDKR V07.02.00.06 and running it on MCU2_0 and MPU1_0)

I was expecting, that the delay for SysBios is significantly smaller than for Linux. However, I observed, that the maximum frequency (On-Off cycle) is

  • 20 MHz (Linux, A72)
  • 1-2 MHz (SysBios using MCU2_0); 5 MHz (SysBios using MPU1_0)

Even writing directly to register GPIO_SET_DATA01 had no significant improving effect on the output frequency. I could only reach a maximum of 2MHz using MCU2_0 (The effect on MPU1_0 was similiar. I never reached the 20 MHz of Linux).

So comparing the output frequency of this GPIO between Linux and SysBios running both an A72 leads to a factor of 4.

Do you have any explanation for this behaviour? Why is a HLOS faster than a RTOS?

Thanks and best regards


  • Hi Felix,

    Regarding the MCU2_0 measurements, lets leave that aside as the MCU core would lkely be running at a lower frequency than the A72, and look at the results of MPU1_0/A72 for Sysbios vs Linux.

    There are many factors at play that can cause the delta, some (not exhaustive) possibilities are listed below:

    • System setup - What is the clock speed of the A72?  Is cache enabled? What else is running on the system?  Are both cores enabled etc
    • Compiler options - The tools used to build the test code and supporting libraries will be subject to the toolset optimizations
    • Test code - Is the test code using interrupts?  Is it a while loop with a delay?  The code under test can impact results. 

    Depending on the requirement, please also be aware of the ePWM (enhanced pulse width modulation) module on the TDA4VM.



  • Hi KB,

    thanks for your reply. I think, as a first step, the most promising factor to investigate would be the clock speed of the A72, since I used a while loop for both cases and the build options were all set to the default ones (default makefile for led_blink and also default makefile for the linux kernel).

    According to this thread, ( the default clock speed of the A72 for linux is 2GHz. Unfortunately, I was not able to find a way to detect the speed for the SysBios application. 

    Is there any tool in CCS or some register I can read which tells me the clock speed of the A72?

    Thanks again for your help and best regards,


  • Hi Felix,

    One options is the 'k3conf' utility, which is available to be run from the Linux command prompt. Run as below see the A72 clock frequency:

    •  k3conf dump clocks 202
    •  k3conf dump clocks 203