Other Parts Discussed in Thread: ASH
Hi Team,
We are using DRA722-GP ES2.0 in one board and facing crash of the application when it is brought up. With the same image having DRA722-GP ES1.0 (CPU Revision 1.0), we are able to boot the image. Any specific changes for the SPI interface or PCIe interface patches we are missing in DRA722 CPU revision 2.0 ? Attached the logs for the reference. We are using kernel version of 4.14.115
UBOOT Logs:
========================================
U-Boot SPL 2017.03 (Dec 18 2020 - 11:12:58)
DRA722-GP ES2.0
Starting boot time counter ... complete.
SPL essential peripherals initialized ...
Trying to boot from SPI
U-Boot 2017.03 (Dec 18 2020 - 11:12:58 +0000)
CPU : DRA722-GP ES2.0
Board: Hirschmann AM57xx based family
Watchdog enabled
I2C: ready
DRAM: 512 MiB
Relocation Offset is: 1f73a000
Now running in RAM - U-Boot at: 9ff3a000
NAND: MODIFIED ECC 128 MiB
MMC: OMAP SD/MMC: 0
Using default environment
In: serial
Out: serial
Err: serial
***** PMIC DEBUG INFO *****
PMIC_VID: 0x5104
PMIC_PID: 0x1709
*** END PMIC DEBUG INFO ***
CHIPSERIAL# 1801e0107fc802e1
***** SPI ONE TIME INIT *****
CPLD Device ID = 0x0012
CPLD Revision = 0x7467
USB hub out of reset = 0x0000
***** END SPI ONE TIME INIT *****
cpu code: 0x1b9bc02f
Net: <ethaddr> not set. Validating first E-fuse MAC
eth0 MAC = A8:10:87:92:46:20
eth1 MAC = A8:10:87:92:46:21
Could not get PHY for cpsw: addr 1
cpsw
Peripherals initialized ...
Hit any key to stop autoboot: 0
========================================
/*------------------------------*/
/* Output of cat /proc/cpuinfo */
/*------------------------------*/
processor : 0
model name : ARMv7 Processor rev 2 (v7l)
BogoMIPS : 12.29
Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc0f
CPU revision : 2
Hardware : Generic DRA72X (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
/*---------------------------------*/
/* Output of cat /proc/interrupts */
/*---------------------------------*/
CPU0
17: 0 CBAR 32 Level gp_timer
20: 43624 GIC-0 27 Level arch_timer
22: 0 CBAR 4 Level l3-dbg-irq
23: 0 WUGEN 10 Level l3-app-irq
25: 1 CBAR 232 Level dra7xx-pcie-main
26: 0 CBAR 233 Level dra7-pcie-msi
27: 1 CBAR 121 Level talert
29: 5283 CBAR 8 Level omap-dma-engine
32: 0 CBAR 361 Level 43300000.edma_ccint
34: 0 CBAR 359 Level 43300000.edma_ccerrint
37: 0 CBAR 24 Level 4ae10000.gpio
38: 0 CBAR 25 Level 48055000.gpio
39: 0 CBAR 26 Level 48057000.gpio
40: 0 CBAR 27 Level 48059000.gpio
41: 0 CBAR 28 Level 4805b000.gpio
42: 0 CBAR 29 Level 4805d000.gpio
43: 0 CBAR 30 Level 48051000.gpio
44: 0 CBAR 116 Level 48053000.gpio
...
Thanks,
Harivignesh GS