• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 102 subscribers
  • Views 357 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6455: Poblem with initializing the McBSP interface

Vladimir Byzov
Prodigy 90 points
Part Number: TMS320C6455

Hi!

I have the problem while initializing the McBSP0 in TMS320C6455 processor.

The initial state of McBSP0 interface (read from PERSTAT0) is "Static Powerdown" (011). According to the SPRU580G the McBSP0 cannot have this state, but only Disabled / Enabled. Trying to initialize the interface by setting the corresponding bit in PERCFG0 gives nothins. Bit in PERCFG0 is in right position ("1"), but the status (continious reading the PERSTAT0 register) is still "Static Powerdown"...

Also the McBSP1 was initially disabled through the statrtup sequence (AEA5 pin). Enabling the McBSP1 didn't help to solve the problem Both (BOTH now!) interfaces are held in "Static Powerdown" state.

Master clock generator is 50 MHz. PLL is configured fot 1 GHz main clock. But the current problem persistd just after reset (before PLL setup) and it seems not ot be related with clocks.

All processor's power pins are connected strictly in accordance to SPRS276J, except following pins:

1. DV DDR (1.8-V I/O supply voltage (SRIO regulator supply). NOTE: If  Rapid I/O is not used, this pin can be connected directly to VSS)

2. DV DDRM (SRIO interface supply: 1.25-V core supply voltage (-1000 and -1200 devices) DVDDRM S 1.2-V core supply voltage (-850 devices). V17 The source for this supply voltage must be the same as that of CVDD. NOTE: If RapidIO is not used, these pins can be connected directly to VSS)

3. DV DD12 (Main SRIO supply: 1.25-V I/O supply voltage (-1000 and -1200 devices) DVDD12 S 1.2-V I/O supply voltage (-850 devices). W18 Do not use core supply. NOTE: If RapidIO is not used, these pins can be connected directly to VSS)

4. DV DD15 ( RGMII / EMAC )

5. AV DDA (SRIO analog supply NOTE: If Rapid I/O is not used, these pins can be connected directly to VSS)

6. AV DDT (SRIO termination supply. NOTE: If RapidIO is not used, these pins can be connected directly to VSS)

7.  VREF HSTL ( RGMII / EMAC )

All above pins are connected to ground as SRIO interface and RGMII EMAC mode are not used. I haven't found any specific information for powering McBSP interface, so I don't know if this powering scheme is correct.

So, the question - what can be wrong with these interfaces and how to start them (I just need the McBSP0). Thank you

  • 0
    TI__Mastermind 29270 points

    Hi,

    I've begun to look into your issue with McBSP0 stuck in "Static Powerdown"

    Are you supplying a clock to the CLKS pin?

    Do you have any way to try ungrounding those supplies that are connected to ground? Do you have any other board with these pins not grounded, like the EVM?

    I would like to make sure you are able to see these bits reflect "enabled state" on a known working board. And then compare differences from there.

    Does the EMACSTAT bitfield behave the same way as McBSP0 (and McBSP1 when you enable it)? Stuckin "Static Powerdown" We know the EMAC supply is grounded.

    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    Prodigy 90 points

    Sorry to us, but all boards we have are made with similar schematic. And as you understand - no possibility to unground shown power pins they are directly (under balls) connected to ground plane.

    About PERSTAT0 - it has the value of 0x03608200. It means:

    HPISTAT - 0 (disabled)

    McBSP0 - 3 (static powerdown)

    McBSP1 - 3 (static powerdown)

    I2CSTAT - 0 (disabled)

    GPIOSTAT - 1 (enabled)

    TIMER1STAT - 0 (disabled)

    TIMER0STAT - 1 (enabled)

    EMACSTAT - 0 (disabled)

    About EMAC. Current situation is shown before EMAC initialization. We did not use RGMII, so there is no problem with installing EMAC with current powering scheme,.

    About McBSP clocks - all pins of McBSP are connected to FPGA. The idea was to use the internal processor's clock. But due to the module status I cannot set the proper mode for McBSP0. Should I set initial clocks to any McBSP clocks for proper initializing?

  • 0 in reply to Vladimir Byzov
    TI__Mastermind 29270 points

    So with the McBSP0 - 3 (static powerdown), you are unable to access the McBSP registers, correct?

    Confirm you are unable to read the CLKSM bit in SRGR register.

    Confirm you are unable to read the GRST bit in SPCR register.

    Is there any way you can provide a clock to CLKS pin (input only) as a debugging measure?

    How are you writing to the PERCFG0 register to enable McBSP0CTL? Do you unlock PERLOCK as described in the below note?

    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    TI__Mastermind 29270 points

    What is the value of bit 12 in Device Status Register (DEVSTAT) - 0x02A8 0000?

    It should be 0 = McBSP1/GPIO and McBSP0 pin functions are enabled (default)

    The default should be 0b0 for this bit. This is controlled by configuration pin AEA7, which should have a pull-down resistor applied.  If it is 0b1 instead, McBSP1/GPIO pin functions are disabled.  

    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    Prodigy 90 points

    Dear friend! Please, tell me, WHERE have you got this information about AEA7 and the 12-th bit of DEVSTAT register? I'm using current documentation for TMS320C6455 and it showes, that 12-bit is Reserved (current value from my project is "1"), and the AEA7 is only the adddress bit - no any relations with McBSP!

    Please, confirm, that you information is correct!

  • +1 in reply to Vladimir Byzov
    TI__Mastermind 29270 points

    Hi,

    The C6455 datasheet reads for AEA7: "IPD... For proper C6455 device operation, do not oppose the IPD on this pin."
    Bit 12 of the DEVSTAT register is Reserved.

    The C6455 device is a reduced feature set from the TCI6482 DSP. In the TCI6482 datasheet, Bit 12 of the DEVSTAT register is VLYNQ_EN.

    The TCI6482 datasheet requires AEA7 to be logic low for McBSP1/GPIO and McBSP0 pin functions. If AEA7 is logic high then McBSP1/GPIO and McBSP0 pin functions are disabled.

    See below pictures.

    TI website no longer offers direct download of the TCI6482 datasheet, but it is archived at other websites.
    https://www.alldatasheet.com/datasheet-pdf/pdf/193152/TI/TMS320TCI6482.html



    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    Prodigy 90 points

    Great (much more great, than it can be imagined!) thanks. Going to update PCB...