This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] DRA821U: How to change the frequency of A72 and R5F cores and disable one A72 core

Part Number: DRA821U
Other Parts Discussed in Thread: DRA829, DRA821

How do I change the frequency of A72 and Main R5F core in DRA821/DRA829 on both RTOS/SBL and Linux/SPL bootflow ? and disable one A72 core in Uboot ?



  • Changing Frequency in the SBL bootflow:

    Using the RTOS/SBL bootflow, one can change the frequency of Main R5F cores by using the API Sciclient_pmSetModuleClkFreq() which then sets up the underlying TI SCI messages parameters.

    An example for setting up processor boot core with the desired clock frequency (before we boot it) in the SBL code: ti/boot/sbl/soc/k3/sbl_slave_core_boot.c

    To use this Sciclient API, look up the DEV ID (this is NOT the host id) of the core that needs to be configured, then look up the related CLK ID for the main processor clock that corresponds, and then set the clk frequency.

    Example values for each core are shown here in this other file (example here for the A72 core values): ti/boot/sbl/soc/k3/sbl_soc_cfg.h

    Changing Frequency in the Uboot/SPL bootflow:

    To change the frequency of A72 to say 400Mhz, use the following Uboot patch


    To change the frequency of Main R5F core in SPL bootloader, use the following patch which modifies the DTS to change frequency in R5F node


    Disabling A72 core in Uboot:

    To disable a core use the following patch in Uboot