Processors forum - Recent Threads

AM6442: GPMC timing data setup

Nathan Mayes — Fri, 19 Jun 2026 17:17:55 GMT

Part Number: AM6442

We are using an FPGA as a NOR memory interface to the AM6442 through the GPMC interface.

The speed we are running the GPMC is very slow speed and the datasetup time specified in the technical reference manual on page 8597 does not make sense too me.

Quoted "Data setup time (GPMC side): Ensures a good capture of a burst of data (as opposed to taking a burst of data out). One word of data is processed in one clock cycle (T = 9.615 ns). The read access time between two bursts of data is tBACC = 5.2 ns. Therefore, data setup time is a clock period – tBACC = 4.415 ns of data setup "

If my period is 30.3ns, that would mean that the data setup time reading from the FPGA 25.1ns (FPGA Tsu, or a to c) with a hold time of exactly 5.2ns (d to c)?

There appears to be no margin for either datasetup (25.1ns) or data hold (5.2ns) for the AM6442 when reading from an external memory.

What is the required data setup and data hold for the AM64x when reading from an external memory device based on?

AM6442: Can't set clock of WWDT(RTI) on A53 core.

Taro Takeda — Fri, 19 Jun 2026 16:51:54 GMT

Part Number: AM6442

Hello TI experts,

I set the frequency passed to the API (SOC_moduleSetClockFrequency) to 25 MHz to set the RTI period to 80 msec, but no interrupt was triggered.

When I configured it the same way on the R5F, the interrupt was triggered.
Does the A53 require additional configuration?

I have attached the source code.
main.c

In the block labeled "Configuration," I have defined the target core and clock settings.
Also, the interrupt handler is `watchdogCallback`.

Please let me know if you have any information.

Regards,

TAKEDA Taro

AM263P4: BISS-C example: bissc_diagnostic_single_channel_am263px-lp_r5fss0-0_freertos_ti-arm-clang

Danilo A. — Fri, 19 Jun 2026 12:43:52 GMT

Part Number: AM263P4
Other Parts Discussed in Thread: TMDSCNCD263P, TMDSHSECDOCK, SYSCONFIG

Hi Team,

Posting on behalf of our customer.

I'll share this E2E post with our customer so he can reply when needed.

I have the following configuration:

Ubuntu 24.04.4 LTS
Prozessor TI AM263P4
Texas Instruments XDS110 USB Debug Probe (TMDSCNCD263P)
Docking Board (TMDSHSECDOCK)
Code Composer Studio (CCS) v12.8.1
TI ARM CLANG v3.2.2.LTS
MCU+ Software Development Kit (SDK) v10.02.00.15
Motor Control SDK v10.02.00.11
SysConfig v1.23.0

I have general questions about the following SDK example for the BISS-C interface: bissc_diagnostic_single_channel_am263px-lp_r5fss0-0_freertos_ti-arm-clang

1) BISSC Position Encoder --> BISSC_CHANNEL1_CLK, BISSC_CHANNEL1_TX, BISSC_CHANNEL1_RX
Does the example run if I connect CLK and RX (my use case) but not the TX pin (used in the daisy chain design only)?
2) GPIOs --> ENC1_EN, CONFIG_GPIO3
What is the purpose of these GPIOs in the example?
3) I2C --> I2C Clock Pin, I2C Data Pin
What is the purpose of these pins and this connection? For a temperature sensor?
4) PRU (ICSS)
Would it be possible to use SPI instead? I could not find any example for this.

Regards,

Danilo

DRA821U-Q1: eMMC selection for DRA821

Max Chen1 — Fri, 19 Jun 2026 12:19:50 GMT

Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821

Hi,

Currently we are using eMMC: Micron : MTFC32GBCAQTC-AAT

and need to use Sandisk: SDINBDA6-32G-ZA, did you see any issue to use Sandisk part ?

Thanks

Max

TDA4VH-Q1: flickering issue in one cam from ldc node

Basil Kuriakose — Fri, 19 Jun 2026 06:50:07 GMT

Part Number: TDA4VH-Q1

i m using 2 camera one 5b cam and one 8b cam conversion of color convert node by using ldc .5b cam is working and for 8b cam flicker issue is there.

obj->colorConvertNode = tivxVpacLdcNode(

obj->graph,

obj->ldcConvertCfg, /* configuration */

NULL, /* warp_matrix — no geometric warp */

obj->ldcConvertRegion, /* region_prms */

NULL, /* mesh_prms — no mesh */

NULL, /* mesh_img — no mesh */

NULL, /* dcc_db — no DCC */

uyvy_in, /* in_img UYVY */

nv12_out, /* out0_img NV12 */

NULL); /* out1_img — single output */

printf("[LDC-8B] tivxVpacLdcNode: %s\n",

obj->colorConvertNode ? "OK" : "FAIL — NULL");

any debug steps can you suggest

TDA4VM: TDA4VM: Need support on YOLOP source compilation using TIDL and deployment on TDA platform

Nandhakumar Shanmugam — Fri, 19 Jun 2026 05:10:16 GMT

Part Number: TDA4VM

Hi,

I am working on deploying a custom YOLOP model on TDA4VM using Processor SDK Linux Edge AI version 11_00_06_00.

https://github.com/hustvl/YOLOP

I would like guidance on the deployment workflow for this model on TDA4VM.

My questions are:

Is YOLOP supported with TIDL on SDK 11_00_06_00?

Can all three output heads (detection, drivable area segmentation, lane segmentation) be accelerated on TDA4VM?

What is the recommended procedure to compile the YOLOP sources using edgeai-tidl-tools?

Are there any reference examples for deploying multi-output ONNX models containing both detection and segmentation outputs?

If some layers are unsupported by TIDL, will they automatically execute on ARM through ONNX Runtime + TIDL Execution Provider?

I have already exported the model to ONNX and would appreciate any deployment guidance, sample configurations, or reference examples.

SDK Version: 11_00_06_00
Platform: SK-TDA4VM / TDA4VM

Looking forward to hear from you ASAP.

Thank you.

Regards
Nandhakumar

66AK2H06: 1Gb SGMII RX initial calibration

Seppo Pyorret — Thu, 18 Jun 2026 17:06:27 GMT

Part Number: 66AK2H06

Hello experts,

We are having issues with rx align errors in 1Gb ethernet and using 66AK2H06 SOC.

My question concerns the initial calibration of serdes during powerup. The silicon errdata SPRZ402F has on pages 84 & 85 a section 'SerDes Fails to Adapt RX BOOST Equalization'. There it explains that the calibration is not done if 8/10b decoding is used. The peripherals listed does not show the 1.25GHz SGMII but the decoding is exactly same 8/10b in 1Gb Ethernet.

According to SPRUHO3A, section 15.3 describes the initial calibration and after PHY startup sequence is complete and it will be done only once. But, taking the silicon errdata into account, is the SOC RX calibrated at all since the 8/10b decoding is being used?

AM62D-Q1: Help interpreting DDR-MARGIN-FW results for pass vs. fail criteria

Jay Coggin — Thu, 18 Jun 2026 15:44:05 GMT

Part Number: AM62D-Q1
Other Parts Discussed in Thread: SYSCONFIG

We are running the DDR-MARGIN-FW tool suite v1.9.0 to evaluate the DDR performance on our custom board based on the AM62D-Q1. So far, we've been successful running the read test, acquiring the measurement logs, and generating the PDF test reports with the included python script. Now, we are trying to establish pass vs. fail criteria for our board using these test reports, but it's not explicit from any documentation we found how to interpret these reports or relate them back to requirements for safe operation. So below is how we are currently interpeting them:

In the LPDDR4 Guidelines for AM62D App Note, Table 3-3 specifies the eye for READ as a diamond with a minimum width and height for a given DDR clock speed. I'm taking these as the spec to meet for our read measurements.

In a simple interpretation of the generated report, I'm guessing our "Worst Delta mV" from the Overview section should be above Read eye mask VdIVW from Table 3-3, and "Worst Delta UI" should be above Read eye mask TdIVW in Table 3-3. Is that a correct interpretation?

Assuming it is, our board fails on the majority of DQ lines at our planned DDR speed of 1866MHz. If we lower the speed to 1600MHz, we pass across all DQ lines relative to the 1600MHz thresholds in Table 3-3.

As a sanity check, I ran the read test on my AM62D EVM using the default EVM DDR configuration. Interestingly, it does not pass this criteria at 1866MHz either. It does appear the voltage margin is stronger on the EVM relative to our board, but both the EVM and our board are bottleknecked by the eye width not meeting spec. I'll attach a PDF report from both the EVM and our board @ 1866MHz.

If my interpretation of these plots is not correct, could you provide any insight on establishing pass/fail criteria? If it is correct, what is the severity of a measurement below the threshold? We have been using our board and the EVM at the 1866MHz clock speed with no perceived issues thus far. Is there any detection and retry mechanism that could be masking these errors?

One note on the attached reports: In order to establish a more apples-to-apples comparison with the spec, we modified the parse_eye_diagrams.py script to compute and overlay the largest diamond that fits in the passing region and added a pass/fail page at the end. This is a stricter requirement, but even just the "Worst Delta mV" and "Worst Delta UI" values fail to meet the Table 3-3 spec.

ddrmargin-read-evm-default-1866.pdf

ddrmargin-read-custom-pcb-1866.pdf

AM62A7-Q1: Capabilities of the Cortex-R5F processor for controlling stepper motors

Evgenii Kuchumov — Thu, 18 Jun 2026 13:32:03 GMT

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: AM62A74, , AM62A7

Hello, colleagues! Could you tell me please about the capabilities of the Cortex-R5F processor (SoC AM62A74-LP) when it comes to working with stepper motors and, particularly, its ability to work with quadrature encoders?

TDA4VEN-Q1: EVM setup for J722S

Shubham Goel — Thu, 18 Jun 2026 13:18:46 GMT

Part Number: TDA4VEN-Q1

Hello Team,

MCAL Package: MCUSW_11_01_00_03_CONFIG-windows-installer.exe + MCUSW_J722S_11.01.00.03.zip

We are working on TDA4VEN/J722S integration activities and working to test TI can_app for CAN Communication.

As part of the EVM setup, We are referring C:\ti\mcu_plus_sdk_j722s_11_01_00_15\docs\api_guide_j722s\EVM_SETUP_PAGE.html for SoC Initialization step but there is no information available for WINDOWS platform:

Can you please provide your feedback on this if we can build and verify TI can_app on WINDOWS?

BR,

Shubham

TDA4VEN-Q1: Trace32 cmm scripts to enable DDR for j722s_cr5

Shubham Goel — Thu, 18 Jun 2026 12:44:41 GMT

Part Number: TDA4VEN-Q1
Other Parts Discussed in Thread: J722SXH01EVM

Hello Team,

We are working on TDA4VEN/J722S integration activities and need to configure DDR region.

Can you please provide example Lauterbach cmm scripts to enable DDR for j722sxh01evm.

BR,

Shubham

J784S4XEVM: unable to dump debug images in multicam application

DARSHAN S — Thu, 18 Jun 2026 12:29:06 GMT

Part Number: J784S4XEVM

Hi team ,

I am running the multicam application and trying to save raw and viss images but not able dump the frames .

I have modified the app_multi_cam.cfg values

# enable writing final output 0-disable, 1-enable

en_out_img_write 1

# enable writing csix output 0-disable, 1-enable

en_out_capture_write 1

# enable writing viss output 0-disable, 1-enable

en_out_viss_write 1

but the ouput path says

# path to write the processed frames
output_file_path /opt/vision_apps/app_cam_out

is it correct ??

need help in dumping the raw and viss frames

Thanks,

Darshan S

AM6421: AM6421 Base Custom Board - Bringing Up PRU Ethernet Interface with DP83822 PHY

Manish Deshmukh — Thu, 18 Jun 2026 09:47:25 GMT

Part Number: AM6421
Other Parts Discussed in Thread: TMDS64EVM

Hi,

We are working on a custom board based on the AM6421 SoC, using Buildroot as our build system with TI's external defconfig. We are using U-Boot version 2026.01.

Our custom board has two Ethernet ports. We are using the TMDS64EVM evaluation board image as the base and modifying the device tree to adapt it for our custom hardware.

We have successfully enabled the PRU Ethernet interface, and the interface (eth0) appears to be up. However, the DP83822 PHY driver is not binding to the PHY. The PHY is instead attached to the Generic PHY driver, and we are unable to ping or establish any network connectivity.

Issue :

Interface eth0 is detected and shows "Link is Up - 100Mbps/Full"
PHY ID reads 0x0000FFFF (invalid)
Driver: Generic PHY instead of TI DP83822
Manual bind attempt fails with "No such device"
NETDEV WATCHDOG timeouts observed

What we have tried:

Loaded the DP83822 driver (modprobe dp83822)
Updated the device tree to set the PHY address to 0x00 on the PRU MDIO bus
Enabled the PRU Ethernet port (status = "okay")
Attempted to manually bind the PHY to the DP83822 driver
Attaching the required files.
ethernet.zip

Regards,

Manish

TDA4VH-Q1: J784S4 and AM69A Processor SDK compatibility

Christophe Van Delsen — Thu, 18 Jun 2026 09:26:33 GMT

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: J784S4XEVM, AM69A

Hello TI Experts,

I have both the J784S4XEVM and SK-AM69A boards on which I want to evaluate SW performance. Can both platforms be supported with a single Processor SDK Linux installation? I lack the disk space to support full Yocto builds on both SDKs individually, and I was wondering whether a single installation can handle both boards. The SDK documentation seems to hint at that by setting the MACHINE variable, e.g.,

MACHINE=<machine> bitbake <target>

Then again, the J784S4 SDK has 11.02.00.04 as latest release, while the AM69A SDK only goes up to 11.00.00.08. So, before I would start the exercise with a single SDK installation, I would like confirmation whether or not a single installation is sufficient. And if so, which SDK version would be most suitable for that?

Kind regards,

Christophe

AM62L: Drive strength of MMC0 line

Parv Patel — Thu, 18 Jun 2026 08:14:29 GMT

Part Number: AM62L

Hii,

I am using AM62Lx board with Linux version: 11.00.15.05
I want to change drive strength of MMC0 I/O line.
How to do it?

Regards,
Parv

AM3358: KGDB support for AM3358 Chipset

Karuppusamy Subiramaniam — Thu, 18 Jun 2026 07:44:14 GMT

Part Number: AM3358

Hi Team,

From the following E2E Ticket we comes to know that KGDB support is not enabled for J784s4 SDK.

PROCESSOR-SDK-J784S4: Support to Enable the KGDB - Aptiv Jacinto Forum - APTIV - EP Automotive - TI E2E support forums

May I Know that Does KGDB support is avilable for Processor SDK Linux for AM335X ?

We have to debug using KGDB during the boot time itself.

Thanks & Regards,

Karuppusamy S

AM623: AM623: What is the minimum supported data rate of the AM623 CAN interface?

yang liu61 — Thu, 18 Jun 2026 06:52:54 GMT

Part Number: AM623
Other Parts Discussed in Thread: SYSCONFIG

What is the minimum supported data rate of the AM623 CAN interface? For example, does it support 10Kbps?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1587243/am623-what-is-the-minimum-supported-data-rate-of-the-am623-can-interface/6114465

TDA4AEN-Q1: Few Question About DSP

Gibbs Shih — Thu, 18 Jun 2026 06:51:40 GMT

Part Number: TDA4AEN-Q1
Other Parts Discussed in Thread: FFTLIB

Dear Expert.

Here are some question about TDA4 DSP, I am not familar it, so forward customer's question and post here, need your comment.

Q1: In the CCS compiler folders below,
C:\ti\ccs2040\ccs\tools\compiler\ti-cgt-c7000_5.0.1.LTS\host_emulation\include\c7524-MMA2_256, we observe a header file named c6x_migration.h, which is like a middle layer that converts C6x APIs to C7x ones. It seems to imply C6x-to-C7x migration is supported.
If we developed our application with C6x libraries, would it be possible to migrate it with C7x libraries with any change in the application?

Q2 : Does C7x FFTLIB supports radix-3, mixed-radix, or required non-power-of-two Doppler FFT sizes?

Q3 : Does C7x FFTLIB supports complex-to-complex FFTLIB twiddle-factor generation options?

Thank You.

Gibbs

TRF-LSC-AFE7950EVM: 3D Model / STEP

Idan Hamani — Thu, 18 Jun 2026 06:38:50 GMT

Part Number: TRF-LSC-AFE7950EVM

Hello, I need a 3D or STEP model of the board TRF-LSC-AFE7950EVM with the components on it, please. The model I received from you does not open well, it opens transparently and without components.

Thank you

AM62D-Q1: How can I get distinguished DMA for different channels

Venkata Someswararao Malla — Thu, 18 Jun 2026 05:57:28 GMT

Part Number: AM62D-Q1

Hi TI Experts,

I’m using an AM62D EVM and configuring McASP to receive I2S data from six independent tuners. I plan to use DMA to transfer the raw captured data to userspace. Is it possible to have a dedicated DMA channel for each of the six I2S data lines?

Requirement: Data should be provided only for the shared device node that is opened. If a user connects a single tuner, capture should occur only for that tuner. Currently, with a single DMA channel, I’m capturing data from all tuners and discarding data from unopened ones. I will create shared device nodes for all six tuners, but capture should start only for the tuner whose node is opened.

Regards,

Venkata

AM5716: AM57-HS and AM57-GP shows different behavior to external memory when reboot

Zekun Bai — Thu, 18 Jun 2026 05:55:38 GMT

Part Number: AM5716

Hi team

Customer has a function that writes specific data (0x1000 bytes) to the DDR address 0x9f900000 before a reboot and reads it back afterward. This works correctly on the GP version, but on the HS version, the data gets overwritten. Does the HS version perform a full memory overwrite upon reboot?

The procedure is as follows:

First, reserve memory in the DTS;
Then, write to this reserved memory using the `devmem` or `devmem2` tool;
Finally, read the data back after executing the `reboot` command in Linux.

With this process, the data read back matches the data written on the GP version, whereas on the HS version, the data does not match.

Thanks for explanation.

Zekun

AM6442: Some questions about ODT settings

Kien — Thu, 18 Jun 2026 03:14:11 GMT

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hi Champs,

I have few questions about the ODT settings.

Q1. We followed your advice and modified the DDRSS_PHY_65_DATA and DDRSS_PHY_321_DATA from 0x01CC0B01 to 0x07CC0B07.

Which one enables the ODT during idle and write time of the LPDDR4 DQ and DQS lines?

What is the difference between these and the setting in SysConfig ODT settings (for example, DQ ODT and SOC ODT)?

Q2. When will the SysConfig ODT setting work?

For example, is the DQ ODT only work when the MCU writes the LPDDR4 DRAM?

Then, when the MCU reads data from the DRAM, the DQ ODT will be open load, while the SOC ODT is activated to terminate?

Or are both always working?

Regards,

Kien

AM62L-EVSE-DEV-EVM: SK-AM62P-LP: does MIPI DSI support roration 90?

Vincent Vincent — Thu, 18 Jun 2026 01:56:47 GMT

Part Number: AM62L-EVSE-DEV-EVM
Other Parts Discussed in Thread: AM62P, AM62L

Hi Expert,

I have connected a MIPI DSI OLED panel to the AM62P EVM board, and it is already displaying properly. However, we need to use it in landscape mode, which requires a 90-degree rotation. I have already configured this in the device tree, but it does not seem to take effect. Could you help me?

The DSI configuration is as follows:

panel@0 {
reg = <0>;
compatible = "visionox,sd3106";
pinctrl-names = "default";
pinctrl-0 = <&main_dsi0_pins_default>;

//backlight = <&vcc_3v3_sys>;
//power-supply = <&vcc_3v3_sys>;
//vci-supply = <&vcc_3v3_sys>;
//vddio-supply = <&vcc_3v3_sys>;
enable-gpios = <&main_gpio0 41 GPIO_ACTIVE_HIGH>;
te-gpios = <&main_gpio0 33 GPIO_PULL_UP>;
rotation = <90>;

port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};

In the driver file, inside the sd3106_probe function, I am retrieving the value from the device tree using of_drm_get_panel_orientation:

err = of_drm_get_panel_orientation(dev->of_node, &ili->orientation);
if (err < 0) {
dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
return err;
}

What do I need to do to implement the rotation?

AM3356: endian

Nobuhiko Wasa — Thu, 18 Jun 2026 01:25:28 GMT

Part Number: AM3356

Hi team,

My customer would like to know if AM3356 with Free RTOS can handle the data with big endian. As to the instructions, customer can accept little endian.
Could you please confirm if this is feasible?

Thanks,
Nobuhiko Wasa

AM623: SK-AM62B-P1 PRU DMA Control

Gavin Knopp — Wed, 17 Jun 2026 22:53:11 GMT

Part Number: AM623
Other Parts Discussed in Thread: SK-AM62B-P1

I am working with the SK-AM62B-P1 devkit and attempting to allocate several DMA channels for the UART interfaces using a custom kernel module through the TI k3-udma-glue drivers and pass along the addresses of the allocated ring accelerators to the PRU so it can push host descriptors as needed per transaction.

To support this, I wrote a kernel-module to allocate the DMA channels when a custom device tree node is encountered.

static int udma_probe(struct platform_device *pdev)
{
    struct device *dev = &pdev->dev;
    struct k3_udma_glue_rx_channel_cfg cfg = {0};
    struct k3_udma_glue_rx_channel *rx_channel;
    int index;
    int error;

    dev_info(dev, "UDMA Hardware Bridge Probing...\n");

    cfg.flow_id_base = 0;
    cfg.flow_id_num = 1;
    cfg.flow_id_use_rxchan_id = false;
    cfg.def_flow_cfg = NULL;
    cfg.remote = false;

    // Request channel from TI glue logic
    rx_channel = k3_udma_glue_request_rx_chn(dev, "uart5_udma_rx", &cfg);
    if (IS_ERR(rx_channel)) 
    {
        dev_err(dev, "Failed to request RX channel (ERR: %pe)\n", rx_channel);
        return PTR_ERR(rx_channel);
    }

    error = k3_udma_glue_enable_rx_chn(rx_channel);
    if(error != 0)
    {
        dev_err(dev, "Failed to enable RX channel (ERR: %d)\n", error);
        return error;
    }

    dev_info(dev, "UDMA Hardware Bridge Probing Finished...\n");    

    return 0;
}

custom_dma: custom-dma-controller {
      compatible = “stave,udma-controller”;
      status = “okay”

      dmas = <&main_bcdma 0x4405 0 0>, <&main_bcdma 0xc405 0 0>;
      dmas-names = “uart5_dma_rx”, “uart5_dma_tx”;
};

When calling k3_udma_glue_enable_rx_chn, I run into the following issues:

-EINVAL returned when configuring the dmas node in the device tree based on other samples when taking the form <&main_bcdma 0 0x4405 0>. The k3-udma-glue.c driver expects the PSI-L ID to be first in the list.
-EBUSY returned, it appears to be failing a check win k3_dmaring_request_dual_ring when using the fwd_id

I also attempted to use the remote flag, but that prevents the glue logic from enabling the channel. My understanding is that enabling the channel requires interactions with the TI SCI, and the PRU does not include a TI SCI interface or at least readily accessible drivers.

Is there anything missing in my configuration that would prevent the TI driver from properly allocating the BCDMA RX channel and associated ring buffers?

I followed the steps in 1.2. Building the SDK with Yocto — Processor SDK AM62x Documentation, are there any driver updates or patches that might address this behavior?

yocto_build_info.txt