Processors forum - Recent Threads

TMS570LS1227: TMS5701227CPGEQQ1/F28P650DK6PTP NDA Functional Safety Documentation

Jerrick Taganap — Tue, 10 Nov 2026 16:45:55 GMT

Hi,

I am hoping to get some NDA functional safety documentation for the TMS5701227CPGEQQ1 and F28P650DK6PTP microprocessors. Let me know if I need to make a separate question for each.

AM4377: AM4377: EtherCAT: PRU-ICSS: Industrial Comm: EtherCAT Slave Stops Responding to SDO Requests After CRC Error Bursts

STEFANO BURNELLI — Tue, 10 Nov 2026 14:50:13 GMT

Part Number: AM4377
Other Parts Discussed in Thread: TMDSIDK437X

We developed an EtherCAT slave device based on the Sitara AM4377, derived from the TMDSIDK437x evaluation board from TI.

The firmware is based on an adaptation of PRU-ICSS-EtherCAT_Slave_01.00.10.01 using PDK_am437x_1_0_17. More recently, we updated the Beckhoff EtherCAT stack to version 5.13. The development environment is Code Composer Studio 9.3.

Under normal operating conditions, the slave works correctly with a TwinCAT master. However, we have observed an issue when multiple CRC errors occur due to network disturbances. These errors can lead to bursts of frame loss and retransmissions. In some cases, after such an event, the device stops responding to SDO requests, while PDO communication continues to operate normally and the slave remains in the OP state from the master's perspective.

As a result, TwinCAT marks the device as CoE Offline, but no error messages are reported and no automatic recovery occurs. The only way we have found to restore normal operation is to force a state transition OP → PRE-OP → OP from the master.

Has anyone encountered a similar issue?

Do you have any suggestions on how to diagnose or resolve this problem?

We have to resolve this Issue on the AM4377 EtherCAT Slave Side _ very urgently _ because our Machines stops working without the correct operation of the CoE OnLine .

Thank you and regards

TDA4AH-Q1: TDA4AH-Q1: DDRSS interface issue during high temperature variation

Alexandre L — Tue, 10 Nov 2026 14:46:20 GMT

Part Number: TDA4AH-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hello Experts,

I am currently working with the TDA4AH and a connected LPDDR4 with a rate of 4266MT/s and encountering an issue with temperature trials:

When running tests at a fixed temperature, the LPDDR4 tests pass every time

When starting from a low temperature and slowly increasing it over time, the LPDDR4 interface tests start failing after a significant temperature increase (0 to +60°C for example). A power off/on of the board corrects the issue, which leads me to think a full re-training of the LPDDR4 link could correct this issue as well.

Would you agree with my statement above?
Is there a specific register to start a full re-training of all the parameters? I have tried many of the DDRSS registers and none seemed to work
- If no, could I use DFS betwwen the same frequencies (f1=2133MHz, f2=2133MHz) to start one?
Is there a way to extract the link training results? This would be interesting to analyse the margin that we have on signal integrity

Few information:

The LPDDR4 parameters have been configured using the TI SYSCONFIG tool and are compliant with the memory datasheet.
Worst case timings have been selected for temperature-sensitive parameters, such as t(REFI)

Thank you.

Regards,

Alexandre

SM34020APCM40: Lifecycle forecast

Steve Ford — Tue, 10 Nov 2026 14:13:40 GMT

Part Number: SM34020APCM40

Current status is Production but NRND

We can also use the 5962-9162304MXC and SMJ34020AGBM40

We have been told by a distributor that these share the same die which is EOL

Does that mean that TI can no longer manufacture the die or just that they have no plans to ?

This is for a very specific defense need so we need to know when production stops

AM2434: AM2434 and PSRAM support

Sergej Sergeyuk — Tue, 10 Nov 2026 14:04:39 GMT

Part Number: AM2434

Hello, TI.

We want to use the AM243x in pair with the AS1C8M16PL-70BIN.

I found the 3 yr old thread with the same topic (refered to SDK version 10.1). But seems to me the SDK still doesn't support the stacked PSRAM device.

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1333170/am2431-max-possible-psram-memory-on-gpmc?keyMatch=AS1C8M16PL-70BIN&tisearch=universal_search

Today I'm at the ccs_20_5_0 + mcu_plus_sdk_am243x_12_01_00_33 but still not able to configure CS0 and CS1. The minimal granularity is 16 MB while 8 required to have the continious memory space.

Can you confirm that my understianing is correct and support of the stacked PSRAM still limited?

AM3359: git.ti.com: cgit snapshot downloads return "Unsupported snapshot format" (HTTP 400)

Yegor Yefremov — Tue, 10 Nov 2026 13:59:15 GMT

Part Number: AM3359

Hello,

Tarball downloads from the cgit web interface on git.ti.com no longer seem to
work. For example, the PRU Software Support Package v6.0.1 tarball:

https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/snapshot/pru-software-support-package-v6.0.1.tar.gz

returns HTTP 400 with an HTML page saying:

Unsupported snapshot format: pru-software-support-package-v6.0.1.tar.gz

The other archive formats fail the same way: .tar, .tar.bz2, .tar.xz and .zip
return 400, and .tar.zst returns 503. The tag page
(https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/tag/?h=v6.0.1)
no longer shows any download links. The repository itself is fine: the tree
view loads and "git ls-remote" still lists the v6.0.1 tag.

Other repositories seem to be affected as well. For example, the k3conf
snapshot (https://git.ti.com/cgit/k3conf/k3conf/snapshot/k3conf-0.4.tar.gz)
also returns 400. So snapshots may be disabled for the whole site.

This affects the Buildroot embedded Linux build system. Its
pru-software-support package downloads the v6.0.1 tarball from this URL. For
now, builds still work only because Buildroot keeps a backup copy of the
tarball.

Was disabling cgit snapshots intentional? If not, could they be re-enabled
(at least .tar.gz)? If it was intentional, is there an official download
location for PRU Software Support Package release tarballs that we should
use instead?

Thank you,
Yegor Yefremo

AM5746: AM5746 ICSS_EMAC: Clarification on PRU firmware differences resolving split-frame loss (01.00.00.16 vs 01.00.00.17)

Yuhei Shimizu — Tue, 10 Nov 2026 13:54:41 GMT

Part Number: AM5746

I have a question regarding the PDK for the AM5746.

We are currently using the AM5746 as an EtherCAT master via a master stack.

During EtherCAT I/O communication, we have observed that when the I/O size is configured to a specific value that requires the data to be split across two frames, frame loss occurs.

[Observed Behavior and Test Results]

PDK 1.0.17: When using the ICSS firmware included with PDK 1.0.17, frame loss occurs during the transmission of split frames (i.e., when data is divided into two frames).
Replacing only the ICSS firmware: Within the same PDK 1.0.17 environment, we replaced only the ICSS firmware (PRU firmware) with the version included in PDK 1.0.21 (ICSS_EMAC 01.00.00.17). Testing confirmed that this resolved the frame loss issue.

[Relevant Release Notes]

ICSS_EMAC Low Level Driver (Release: 01.00.00.16 / included with PDK 1.0.17)
ICSS_EMAC Low Level Driver (Release: 01.00.00.17 / included with PDK 1.0.21)

[Question] According to the release notes, the only change listed between version 01.00.00.16 and 01.00.00.17 is as follows:

This release includes: Naming changes for some of the data structures for using more inclusive terminology

However, a comparison of the actual source code reveals numerous differences.

Could you provide a document or a list detailing the changes--such as bug fixes or functional modifications--included in this version update, beyond the aforementioned naming changes? (In particular, I am interested in any changes related to frame transmission/reception and buffer handling.)

If no such documentation is publicly available, could you please specify exactly what functional changes or fixes have been implemented?

AM2634: AM2634 DEBUG CONNECTION ERROR

Baris Bostan — Tue, 10 Nov 2026 13:09:51 GMT

Part Number: AM2634
Other Parts Discussed in Thread: LP-XDS110

Hello,

I am trying to connect to an AM2634 on my custom PCB for debugging using an external LP-XDS110 Debugger. CCS reports a DAP access error when I start debugging. The full message text is:

CS_DAP_0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation.
If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 21.0.0.3955) .

My development setup is as follows:
-MCU part number is AM2634CODFHAZCZR.
-CCS version is 21.0.0.
- I am using LP-XDS110 Debugger to connect to the chip. Debugger is connected through TCK, TMS, TDI, TDO and GND. 3.3V output is not currently connected

Initially, the switches in the SOP selection circuit were configured for DevBoot according to the table shown below. I then tried the inverse configuration, because I was unsure whether the table indicated the switches’ open/closed states or the actual HIGH/LOW logic levels at the MCU’s SOP pins. Nonetheless, CCS reported the same DAP access error in both cases.

I have attached the SOP selection schematic and the boot-mode table below for reference. The pull-up and DNP resistor settings in the schematic were also changed and made compliant to DevBoot configuration.

I would also appreciate clarification on the table issue.

TMS320F280049: TMS320F280049: new section in errata: Flash: Execution of Fapi_setActiveFlashBank() Without Disabling Flash Prefetch may Cause ITRAP

StephanS — Tue, 10 Nov 2026 09:00:35 GMT

Part Number: TMS320F280049

Hi,
I have a question concerning the newest Errata for the TMS320F280049: TMS320F28004x Real-Time MCUs Silicon Errata (Rev. I), Flash: Execution of Fapi_setActiveFlashBank() Without Disabling Flash Prefetch may Cause ITRAP:

It says: "Fapi_setActiveFlashBank() disables the prefetch mechanism."

This is not what I see when debugging our code.

We are running F021_ROM_API_F28004x_FPU32.lib from ROM and are calling it from functions running in RAM. The relevant function Fapi_setActiveFlashBank() is located at 0x003ffefe, in ROM.

The PREFETCH_EN bit in FRD_INTF_CTRL does not seem to be touched by Fapi_setActiveFlashBank(): If it was 0 before, it is 0 after and if it was 1 before, it is 1 after.

So for me, the proposed workaround does not do any harm, but is not really necessary (at least not when running from ROM).

In addition, we do not have any problems with many devices in the field regarding this errata.

Maybe the errata is not for flash API running from ROM?

Thanks in advance.

TDA4AEN-Q1: Do we have any tool (way) to diagnosis LPDDR4 once boot failed

Gibbs Shih — Tue, 10 Nov 2026 08:49:20 GMT

Part Number: TDA4AEN-Q1

Dear Expert,

I try to sumarrize some idea to help customer debug boot failed w/ LPDDR4 issues, so I create this thread.

Here is my previsous experence on AM623x.

Steps as below.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1625035/am625-ddr4-nt5ad256m16e4-jri-initialized-failed-in-tiboot3/6299468?tisearch=e2e-sitesearch&keymatch=%20user%3A533255

(1) I try to dump DDR Register PHY in u-boot

(2) I try to run memtest in u-boot

(3) I try to share LPDDR4 configure file

(3) Depend on item (1) & (2)(3), I try to collect these log file & discussion (+debug) w/ BU expert.

So how about TDA4AEN? Do we have any tool (way) to diagnosis LPDDR4 once boot failed

This is a special case, because customer may not use u-boot as bootloader, that's mean it runs SBL only.

(1) Do we have any *.gel to help customer dump LPDDR4 PHY register w/ JTAG? or

(2) Do we have any test program to help customer dump LPDDR4 PHY register?

(3) Do we have any *.gel to run memory test w/ JTAG

Thank You.

Gibbs

Another ref.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1494324/tda4ven-q1-nanya-ddr-adaptation-issues

AM6421: Processor for Ethernet Gateway

Viktor Schneigelberger — Tue, 10 Nov 2026 08:44:58 GMT

Part Number: AM6421
Other Parts Discussed in Thread: SK-AM64B, TMDS64EVM, AM2432, AM6442, , AM2434

Hello,

For a new project we need besides PROFINET and EtherNet/IP, also EtherCAT, and maybe POWERLINK.

We have the TMDS64EVM and SK-AM64B dev. kits.

So, a few questions:

Is EtherCAT supported on both AM64x and AM243x?

Are F part numbers needed for all three protocols, or only for PROFINET?

Which exact numbers would you suggest for AM2434, AM2432, AM6442 and AM6421?

Are the AM6442 on our kits F parts, so PROFINET will run on them?

And which kit would you take for Linux plus the stack on R5F?

Is there a POWERLINK "Controlled Node" stack from TI, or a partner you would recommend?

The current device from the previous project that we have, passed ODVA CT22.

Which versions of the TI stacks are certified today by ODVA, PI and ETG?

Roughly how much on-chip SRAM do the Profinet and EtherNet/IP stacks take on AM243x?

We also need a web server with TLS next to them.

Regards,

Viktor

AM3352: AM3352, MT29F2G08ABAEAH4-IT/63-BALL, can't boot

kyusang — Tue, 10 Nov 2026 08:20:57 GMT

Part Number: AM3352

I have designed a system using the AM3352 processor with an MT29F2G08ABAEAH4-IT NAND flash for booting. I am encountering an issue that did not occur previously: the system fails to boot, and "cccccc" appears upon power-up. Interestingly, the system boots normally if I add a ~12pF capacitor to the nWE pin, or even just by applying the capacitive load of an oscilloscope probe to that pin. Could you please provide some insight into why this might be happening, or offer any advice?

AM6442: AM6442: MCU+ SDK 12.00.00.27 SA2UL driver ignores IV in AES-CBC mode (engine behaves as IV = 0)

YECHAN LEE — Tue, 10 Nov 2026 05:55:48 GMT

Part Number: AM6442
Other Parts Discussed in Thread: TMDS64EVM, SHA-256

Environment

Device: AM6442 SR2.0 HS-FS (TMDS64EVM, rev D)
SDK: MCU+ SDK for AM64x 12.00.00.27
Core / OS: R5FSS0-0, NORTOS
Compiler: TI Arm Clang 5.1.1.LTS
Base project: examples/security/crypto/sa2ul_pka/rsa_signing_verification (syscfg unchanged)
Boot: DEV BOOT mode, loaded via CCS (load_dmsc_hsfs.js)

Summary
In AES-CBC mode, the SA2UL driver does not apply the IV passed in SA2UL_ContextParams.iv. The engine always behaves as if IV = 0. Encrypt→decrypt round trips succeed, so the bug is not visible with the SDK example crypto_aes_cbc_256. That example only checks the round trip and does not compare the ciphertext against a known-answer vector. AES-ECB, AES-GCM and SHA-256/512 match standard test vectors with the same driver.

Steps to reproduce
Use the NIST SP800-38A F.2.5 vector (CBC-AES256.Encrypt, first block):

Key = 603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4
IV = 000102030405060708090a0b0c0d0e0f
P1 = 6bc1bee22e409f96e93d7e117393172a
Expected C1 = f58c4c04d6e5f1ba779eabfb5f7bfbd6

SA2UL_ContextParams p;
memset(&p, 0, sizeof(p));
p.opType       = SA2UL_OP_ENC;
p.encAlg       = SA2UL_ENC_ALG_AES;
p.encMode      = SA2UL_ENC_MODE_CBC;
p.encKeySize   = SA2UL_ENC_KEYSIZE_256;
p.encDirection = SA2UL_ENC_DIR_ENCRYPT;
memcpy(p.key, key, 32);
memcpy(p.iv,  iv,  16);
p.inputLen = 16;
ctxObj.totalLengthInBytes = 16;
SA2UL_contextAlloc(cryptoCtx.drvHandle, &ctxObj, &p);
CacheP_wb(in, 16, CacheP_TYPE_ALLD);
CacheP_inv(in, 16, CacheP_TYPE_ALLD);
SA2UL_contextProcess(&ctxObj, in, 16, out);
SA2UL_contextFree(&ctxObj);

Expected result
C1 = f58c4c04d6e5f1ba779eabfb5f7bfbd6

Actual result

C1 = f3eed1bdb5d2a03c064b5a7e3db181f8
This equals AES-256-ECB(K, P1), i.e. the CBC result with IV = 0.
The effective IV, computed as AES-ECB-Decrypt(K, C1) XOR P1 on the same device, is 00000000000000000000000000000000.
The full 4-block F.2.5 encrypt and F.2.6 decrypt KATs both fail.
Round trips are self-consistent for all sizes from 16 B to 16 KB.
The same key gives a correct AES-256-ECB result (SP800-38A F.1.5 PASS). Key handling is therefore correct.

Analysis

sa2ul.c L1211: for non-GCM modes, the IV is copied into sc.u.enc.encAux3 via SA2UL_u8LeToU32(). This is the same conversion as the key (L1181).
The whole context is then passed through SA2UL_64bEndianSwap() (L1233).
The key path through the same conversions produces correct ECB output, so the byte/word conversion itself appears correct.
Our hypothesis is that the CBC mode control instructions do not load the IV from encAux3. Alternatively, the IV may be expected elsewhere, for example in the per-packet command label / PS info. For comparison, the Linux kernel sa2ul driver (drivers/crypto/sa2ul.c) passes the CBC IV per request in the command label, not in the security context.
GCM in the same driver works with IV||counter in encAux3 (TI example vector tag matches).

Impact

CBC with a fixed zero IV leaks plaintext patterns: identical leading plaintext blocks give identical ciphertext under the same key.
The output is not interoperable with standard CBC implementations (OpenSSL, Linux CE): the first block decrypts incorrectly.
This matters for our EU Cyber Resilience Act (CRA) compliance work, where we must verify the correctness of third-party crypto components.

Workaround in use

Encrypt: XOR the IV into P1 before calling the driver.
Decrypt: XOR the IV into the first 16 bytes of the output.
This gives standard CBC results while the engine runs with IV = 0.
At init, we run a one-block KAT to detect the engine behavior, so the workaround is not applied twice if the driver is fixed.

Questions

Can TI confirm this is a driver bug in MCU+ SDK 12.00.00.27? Are earlier and later SDK versions affected?
What is the correct way to supply the CBC IV to SA2UL (context field or command label)? Is a patch planned?
Are other non-GCM IV modes affected (CTR/CFB/OFB at the HW level, and AES-CMAC)?
Unrelated but observed: SA2UL_CACHELINE_ALIGNMENT is defined as 16 in sa2ul.h, while the R5F cache line is 32 bytes. Is 16-byte alignment sufficient for SA2UL DMA buffers on R5F?

AM623: FMEA file

Tony Tang — Tue, 10 Nov 2026 03:20:59 GMT

Part Number: AM623

Customer asks forn AM6231 ALW FMEA file, need it include:

#1. Analysis of short circuits between all adjacent pins;

#2. Analysis of short circuits between each pin and VCC or GND.

Can TI provide it?

AM2434: AM2434: EXT_SITMPUSW-301 appears not fixed in MCU+ SDK 12.00.00.26

tamaki kouno — Tue, 10 Nov 2026 02:33:53 GMT

Part Number: AM2434

Hello,

I have a question about EXT_SITMPUSW-301:

“OSPI_norFlashInit1s1s1s has an implementation of wait for 500 milliseconds instead of microseconds.”

This issue is listed as a Fixed Issue in the AM243x MCU+ SDK 12.00.00 release notes, and the SIR indicates:

Found In Release: 12.00.00
Fix In Release: 12.00.00
Resolution: Fixed

However, I installed the official AM243x MCU+ SDK 12.00.00.26 and checked:

source/drivers/ospi/v0/lld/ospi_nor_flash_lld.c

The following code is still present:

 
uint32_t waitMicro = 500U * 1000U;
hOspi->Clock_usleep(waitMicro);

Therefore, the wait time still appears to be 500 ms.

I also checked REL.MCUSDK.K3.12.01.00.33, and the same implementation is present.

Could you please confirm:

Was EXT_SITMPUSW-301 actually fixed in AM243x MCU+ SDK 12.00.00?
If so, which source file and commit contain the fix?
Is the intended fix to change 500U * 1000U to 500U, resulting in a 500 µs delay?

Thank you.

AM2432: External FPGA IRQ is asserted, goes LOW, 130 milli-seconds the IRQ handler is called

Frederick Severson — Tue, 10 Nov 2026 02:26:50 GMT

Part Number: AM2432

There is an FPGA in the design.

the FPGA asserts the IRQ line, goes low.

130 milli-seconds later the ISR handler starts executing.

I cannot locate the reason why there is a large delay from the pin going low to the handler being called.

void FPGA_Irq_0_Init()

{

pinNum0 = INTN_FPGA_GPIO0_19_PIN;

gpioBank0 = GPIO_GET_BANK_INDEX(pinNum0);

gpioPinMask0 = GPIO_GET_BANK_BIT_MASK(pinNum0);

// separated ISR for now, can combine to one,

intrNum0 = INTN_FPGA_GPIO0_19_INTR_NUM;

/* Address translate */

gGpioBaseAddr0 = (uint32_t) AddrTranslateP_getLocalAddr(INTN_FPGA_GPIO0_19_BASE_ADDR);

/* Interrupt 0 */

/* Register pin interrupt - initializing struct members */

HwiP_Params_init(&hwiPrms0);

hwiPrms0.intNum = intrNum0;

hwiPrms0.callback = &fpga_isr0; // ISR 0

hwiPrms0.args = (void *) pinNum0; // only one interrupt trigger

hwiPrms0.priority = 0;

// GPIO interrupt is a pulse type interrupt

// The FPGA may be setup to be a level interrupt, need to verfy

// 0: Map interrupt as level interrupt

// 1: Map interrupt as pulse interrupt, only used with ARM R5, ARM M4

hwiPrms0.isPulse = TRUE;

retVal0 = HwiP_construct(&gGpioHwiObject0, &hwiPrms0);

DebugP_assert(retVal0 == SystemP_SUCCESS );

}

static void fpga_isr0(void *args)

{

IRQ_GPIO_Identifier_toggle(); // toggle

SK-TDA4VM: Can I use the ADC3641 to capture radar data and have the SK-TDA4VM?

eric rk — Tue, 10 Nov 2026 00:42:41 GMT

Part Number: SK-TDA4VM
Other Parts Discussed in Thread: ADC3641, TDA4VM

Hello TI Community,

Can I use the ADC3641 to capture radar data and have the SK-TDA4VM?

Best Regards,
Eric.

AM6422: DMSC Security Handover on AM64x

Dmitri Verechtchiagine — Mon, 09 Nov 2026 18:14:13 GMT

Part Number: AM6422

Hello,

According to the TISCI documentation the Security Handover function is only supported on AM64x. I would like to confirm that TI will always support the Security Handover function on AM64x.

Is there a possibilty that the Security Handover will be supported on other SoCs of K3 family? We may decide to use other SoCs for other products and would like to be able to use the Security Handover function on other products as well.

Thank you.

AM67: AM67

Nicolas Rancher — Mon, 09 Nov 2026 14:41:01 GMT

Part Number: AM67

Hi TI team could you clarify this regarding the AM67 LPDDR4 guidelines?

"Skew across CMD_ADDR, and CTRL and associated CK clock net class = 60ps max" & "Skew across net class DQSx and BYTEx is 25ps max".

Does this truly mean any signal with that group can be 60ps/25ps apart. For instance that CLK to a CAC signal can be 60ps apart or a DQS to a DQ signal can be 25ps apart? Or is the intent that CAC to CLK is +/-30ps max and DQ/DM to DQS to +/-12.5ps max.

SK-AM62P-LP: AM62Px OTP Keywriter: SWREV fields - skip or program before KEYREV=1?

Binil S — Mon, 09 Nov 2026 12:40:27 GMT

Part Number: SK-AM62P-LP

We are provisioning an AM62Px SR1.0 (SK-AM62P-LP) for automotive security (AIS-190 / ISO 21434) using incremental keywriter passes. We have completed Pass 1 (MSV) and Pass 2 (SMPKH + SMEK + BMPKH + BMEK). We are about to run Pass 3 (KEYCNT) and Pass 4 (KEYREV=1 — irreversible HS-SE conversion).

All passes must be completed before KEYREV=1 because the keywriter cannot run on an HS-SE device. We need to decide whether to add SWREV passes before KEYREV.

The contradiction in documentation

The Programmable Keys table in the Introduction section of all keywriter versions (09.01.00, 11.01.00, 11.01.09) explicitly states:

SWREV-SBL:         DO NOT PROGRAM — initial values set by TI
SWREV-SYSFW:       DO NOT PROGRAM — initial values set by TI
SWREV-BOARDCONFIG: DO NOT PROGRAM — initial values set by TI

However, the Reference Commands section of the same document provides these as part of the incremental programming sequence:

./gen_keywr_cert.sh -t tifek/SR_10/ti_fek_public.pem \
  --sr-sbl 1 --sr-sysfw 1 --sr-sysfw-ovrd --sr-sbl-ovrd

./gen_keywr_cert.sh -t tifek/SR_10/ti_fek_public.pem \
  --sr-bcfg 1 --sr-bcfg-ovrd

The AM62X 11.01.07 guide adds an additional note not present in the AM62Px guide: "The current software revision of SYSFW, SBL and BCFG is already 1. These fields do not need to be programmed now." This implies TI pre-sets SWREV to 1 — but we need this confirmed for AM62Px SR1.0 specifically.

Additionally, our U-Boot source sets bcfg_header->sw_rev = 0 in the board config builder:

/* u-boot/arch/arm/mach-k3/r5/sysfw-loader.c */
bcfg_header->num_elems = 2;
bcfg_header->sw_rev = 0;

Q1: Skip or program SWREV for AM62Px SR1.0?

For a fresh HS-FS AM62Px SR1.0 device being provisioned for the first time, should SWREV fields be programmed via the keywriter or skipped entirely? The "DO NOT PROGRAM" note and the reference commands section contradict each other.

Q2: Consequence of skipping SWREV

If we skip SWREV programming entirely and convert to HS-SE, what SWREV value does ROM enforce for anti-rollback? Will our Android 11.00.00 bootloader images boot without SWREV mismatch errors on the HS-SE device?

Q3: SWREV management after HS-SE conversion

Once the device is HS-SE (KEYREV=1), the keywriter cannot run again. Can SWREV be incremented in the field via a TISCI message (e.g. TISCI_MSG_SET_SWREV), or does SWREV management on HS-SE devices require a different mechanism?

References

Package: otp_keywriter_am62px_v11_01_09 (AM62Px SR1.0, mySecureSW)
SYSFW: v11.01.05d "Fancy Rat", ABI 4.0, revision 0x000b
Android SDK: Processor SDK Android for AM62Px 11.00.00
Hardware: SK-AM62P-LP, AM62Px SR1.0
TISCI Key Writer guide: https://software-dl.ti.com/tisci/esd/latest/6_topic_user_guides/key_writer.html

SK-AM62P-LP: AM62Px OTP Keywriter : Cust MPK Hash zero in SoC ID after SMPKH programmed, expected before KEYREV?

Binil S — Mon, 09 Nov 2026 12:34:06 GMT

Part Number: SK-AM62P-LP

Board: SK-AM62P-LP · AM62Px
Processor SDK Android 11.00.00 · AAOS 16 · Keywriter v11.01.09

We are provisioning an AM62Px SR1.0 device (SK-AM62P-LP) running AAOS 16 for automotive security (AIS-190 / ISO 21434) using keywriter package otp_keywriter_am62px_v11_01_09 with PKCS#8 RSASSA-PSS keys.

We are using incremental (multi-pass) programming. Each pass generates a separate x509 certificate, rebuilds tiboot3.bin, and boots it on a spare HS-FS board via UART. Our pass sequence is:

Pass 1 — MSV: programmed MSV = 0xC0FFE. Confirmed via M4F log.
Pass 2 — SMPKH + SMEK + BMPKH + BMEK: all 4 key hashes confirmed matching verify_hash.csv. M4F log showed "Programmed 11/11 rows" and "Programmed 2/2 rows" for each key field. No errors.
Pass 3 — KEYCNT: pending — blocked on SWREV question below.
Pass 4 — KEYREV = 1: pending — this is the irreversible HS-SE conversion step.

After completing Pass 2 (SMPKH + SMEK + BMPKH + BMEK successfully programmed), we ran parse_uart_boot_socid.py in UART boot mode. The SoC ID output showed:

DeviceType    : HSFS
Key Revision  : 0
Key Count     : 0
Cust MPK Hash : 0000000000000000000000000000000000000000...  (all zeros)

Is Cust MPK Hash = zeros in the SoC ID expected behavior at this stage?

Our understanding is that the ROM only reports the active customer key in the SoC ID after KEYREV is set to 1. Before KEYREV=1, the SMPKH is physically present in eFuse but not yet activated as the root of trust, so the ROM reports zeros. After KEYREV=1 (Pass 4), the SoC ID will show the actual SMPKH value and DeviceType will change to HSSE.

Please confirm whether this interpretation is correct, or whether zeros in Cust MPK Hash after Pass 2 indicates a programming error that must be investigated before proceeding to Pass 3 and Pass 4.

Package: otp_keywriter_am62px_v11_01_09 (AM62Px SR1.0, mySecureSW)
SYSFW: v11.01.05d "Fancy Rat", ABI 4.0, revision 0x000b
Android SDK: Processor SDK Android for AM62Px 11.00.00
Hardware: SK-AM62P-LP, AM62Px SR1.0

SK-AM62P-LP: Android DSS Disply sharing HDMI disply for both A53 and WKUP R5

Shanooj P P — Mon, 09 Nov 2026 11:00:36 GMT

Part Number: SK-AM62P-LP

Hi ,

Following up on this thread Link

I now want a second Android display on DSS1, using an IT6263 LVDS-to-HDMI converter:
DSS1 -> OLDI TX1 (single link) -> IT6263 -> HDMI monitor, 1920x720

What I did
- Followed SPRADS3 section 4.3 for DSS1 -> OLDI TX1 (clocks 235/241, oldi1_dss1)
- IT6263 is on I2C0 (0x4c), plugged into J27
- The same IT6263 board works when driven from DSS0 -> OLDI TX0

What happens
- Android renders to the display, but the HDMI monitor is black
- Linux sees the HDMI connector and reads EDID through the IT6263
- IT6263 reports "failed to wait for video stable"

How do i enable the DSS1 with IT6263 bridge to hdmi?

Thanks.

base dt : k3-am62p5-sk.dts

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree file for the AM62P5-SK
 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Schematics: www.ti.com/.../sprr487
 */

/dts-v1/;

#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62p5.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>	
#include "k3-pinctrl.h"

/ {
	compatible = "ti,am62p5-sk", "ti,am62p5";
	model = "Texas Instruments AM62P5 SK";

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart0;
		serial3 = &main_uart1;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		mmc2 = &sdhci2;
		spi0 = &ospi0;
		ethernet0 = &cpsw_port1;
		ethernet1 = &cpsw_port2;
		usb0 = &usb0;
		usb1 = &usb1;
	};

	chosen {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		stdout-path = &main_uart0;

		framebuffer0: framebuffer@0 {
			compatible = "simple-framebuffer";
			power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&k3_clks 186 6>,
				 <&dss0_vp1_clk>,
				 <&k3_clks 186 2>;
			display = <&dss0>;
			status = "disabled";
		};
	};

	memory@80000000 {
		/* 8G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
		      <0x00000008 0x80000000 0x00000001 0x80000000>;
		device_type = "memory";
		bootph-pre-ram;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x24000000>;
			linux,cma-default;
		};

		rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b500000 0x00 0x00300000>;
			no-map;
		};

		mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b800000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b900000 0x00 0xf00000>;
			no-map;
		};

		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9c800000 0x00 0x100000>;
			no-map;
		};

		wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9c900000 0x00 0x1e00000>;
			no-map;
		};

		secure_tfa_ddr: tfa@9e780000 {
			reg = <0x00 0x9e780000 0x00 0x80000>;
			no-map;
		};

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			no-map;
		};

		carveout_video: video {
			compatible = "dma-heap-carveout";
			reg = <0x00 0xa0000000 0x00 0x29000000>;
			no-map;
		};
	};

	vmain_pd: regulator-0 {
		/* TPS65988 PD CONTROLLER OUTPUT */
		compatible = "regulator-fixed";
		regulator-name = "vmain_pd";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
		bootph-all;
	};

	vcc_5v0: regulator-1 {
		/* Output of TPS630702RNMR */
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
		bootph-all;
	};

	vdd_mmc1: regulator-2 {
		/* TPS22918DBVR */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
		bootph-all;
	};

	vddshv_sdio: regulator-3 {
		compatible = "regulator-gpio";
		regulator-name = "vddshv_sdio";
		pinctrl-names = "default";
		pinctrl-0 = <&vddshv_sdio_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
		bootph-all;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&usr_led_pins_default>;

		led-0 {
			label = "am62-sk:green:heartbeat";
			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
			function = LED_FUNCTION_HEARTBEAT;
			default-state = "off";
		};
	};

	opp-table {
		/* Requires VDD_CORE at 0v85 */
		opp-1400000000 {
			opp-hz = /bits/ 64 <1400000000>;
			opp-supported-hw = <0x01 0x0004>;
			clock-latency-ns = <6000000>;
		};
				
		/* Add 1.6GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v89 */
		opp-1600000000 {
			opp-hz = /bits/ 64 <1600000000>;
			opp-supported-hw = <0x01 0x0004>;
			clock-latency-ns = <6000000>;
		};
	};

	tlv320_mclk: clk-0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <12288000>;
	};

	codec_audio: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "AM62x-SKEVM";
		simple-audio-card,widgets =
			"Headphone",	"Headphone Jack",
			"Line",		"Line In",
			"Microphone",	"Microphone Jack";
		simple-audio-card,routing =
			"Headphone Jack",	"HPLOUT",
			"Headphone Jack",	"HPROUT",
			"LINE1L",		"Line In",
			"LINE1R",		"Line In",
			"MIC3R",		"Microphone Jack",
			"Microphone Jack",	"Mic Bias";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp1>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&tlv320_mclk>;
		};
	};

	hdmi0: connector-hdmi {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = "a";
		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&sii9022_out>;
			};
		};
	};

	wlan_lten: regulator-30 {
		compatible = "regulator-fixed";
		regulator-name = "wlan_lten";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vdd_mmc1>;
		gpios = <&exp1 11 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	wlan_en: regulator-31 {
		compatible = "regulator-fixed";
		regulator-name = "wlan_en";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&wlan_lten>;
		enable-active-high;
		gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&wlan_en_pins_default>;
	};
	
	transceiver1: can-phy0 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};

	transceiver2: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};

	transceiver3: can-phy2 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};

	transceiver4: can-phy3 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};
};

&main_gpio0 {
	bootph-all;
};

&main_gpio1 {
	bootph-all;
};

&main_pmx0 {
	bootph-all;

	main_i2c0_pins_default: main-i2c0-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */
			AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */
			AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */
		>;
		bootph-all;
	};

	main_i2c2_pins_default: main-i2c2-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
			AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
		>;
	};

	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C22) UART0_RTSn.GPIO1_23 */
		>;
	};

	main_mcasp1_pins_default: main-mcasp1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
			AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */
			AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
			AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */
		>;
	};

	main_mdio1_pins_default: main-mdio1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
			AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
		>;
		bootph-all;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */
			AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */
			AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */
			AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */
			AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */
			AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */
			AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */
		>;
		bootph-all;
	};

	main_mmc2_pins_default: main-mmc2-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */
			AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */
			AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
			AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */
			AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
			AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
			AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
		>;
		bootph-all;
	};

	main_rgmii1_pins_default: main-rgmii1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
			AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
			AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
			AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
			AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
			AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
			AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
			AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
			AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
			AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
			AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
			AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
		>;
		bootph-all;
	};

	main_rgmii2_pins_default: main-rgmii2-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */
			AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */
			AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */
			AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */
			AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */
			AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */
			AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */
			AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */
			AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */
			AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */
			AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */
			AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */
		>;
		bootph-all;
	};

	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x1c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
			AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
		>;
		bootph-all;
	};

	main_uart1_pins_default: main-uart1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */
			AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */
			AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */
			AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */
		>;
		bootph-all;
	};

	main_usb1_pins_default: main-usb1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */
		>;
	};

	main_wlirq_pins_default: main-wlirq-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0128, PIN_INPUT, 7) /* (K25) MMC2_SDWP.GPIO0_72 */
		>;
	};

	ospi0_pins_default: ospi0-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */
			AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */
			AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */
			AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */
			AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */
			AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */
			AM62PX_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */
			AM62PX_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */
			AM62PX_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */
			AM62PX_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */
			AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */
		>;
		bootph-all;
	};

	usr_led_pins_default: usr-led-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */
		>;
	};

	vddshv_sdio_pins_default: vddshvr-sdio-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */
		>;
		bootph-all;
	};

	wlan_en_pins_default: wlan-en-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x124, PIN_OUTPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */
		>;
	};

	main_dpi_pins_default: main-dpi-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0100, PIN_OUTPUT, 0) /* (W20) VOUT0_VSYNC */
			AM62PX_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AC20) VOUT0_HSYNC */
			AM62PX_IOPAD(0x0104, PIN_OUTPUT, 0) /* (Y21) VOUT0_PCLK */
			AM62PX_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (W21) VOUT0_DE */
			AM62PX_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (AE24) VOUT0_DATA0 */
			AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA1 */
			AM62PX_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA2 */
			AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA3 */
			AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (AB23) VOUT0_DATA4 */
			AM62PX_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (AD23) VOUT0_DATA5 */
			AM62PX_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (AC23) VOUT0_DATA6 */
			AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AE23) VOUT0_DATA7 */
			AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AE22) VOUT0_DATA8 */
			AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AC22) VOUT0_DATA9 */
			AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */
			AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AE21) VOUT0_DATA11 */
			AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AD21) VOUT0_DATA12 */
			AM62PX_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AC21) VOUT0_DATA13 */
			AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA20) VOUT0_DATA14 */
			AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y20) VOUT0_DATA15 */
			AM62PX_IOPAD(0x005c, PIN_OUTPUT, 1) /* (AC25) GPMC0_AD8.VOUT0_DATA16 */
			AM62PX_IOPAD(0x0060, PIN_OUTPUT, 1) /* (AB25) GPMC0_AD9.VOUT0_DATA17 */
			AM62PX_IOPAD(0x0064, PIN_OUTPUT, 1) /* (AA25) GPMC0_AD10.VOUT0_DATA18 */
			AM62PX_IOPAD(0x0068, PIN_OUTPUT, 1) /* (W24) GPMC0_AD11.VOUT0_DATA19 */
			AM62PX_IOPAD(0x006c, PIN_OUTPUT, 1) /* (Y24) GPMC0_AD12.VOUT0_DATA20 */
			AM62PX_IOPAD(0x0070, PIN_OUTPUT, 1) /* (AD25) GPMC0_AD13.VOUT0_DATA21 */
			AM62PX_IOPAD(0x0074, PIN_OUTPUT, 1) /* (AB24) GPMC0_AD14.VOUT0_DATA22 */
			AM62PX_IOPAD(0x0078, PIN_OUTPUT, 1) /* (AC24) GPMC0_AD15.VOUT0_DATA23 */
			AM62PX_IOPAD(0x009c, PIN_OUTPUT, 1) /* (AD24) GPMC0_WAIT1.VOUT0_EXTPCLKIN */
		>;
	};

	main_epwm0_pins_default: main_epwm0-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (D20) SPI0_CS0.EHRPWM0_A */
			AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */
		>;
	};

	main_epwm1_pins_default: main_epwm1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (B21) SPI0_CLK.EHRPWM1_A */
			AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 2) /* (B20) SPI0_D0.EHRPWM1_B */
		>;
	};

	main_ecap1_pins_default: main_ecap1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (E24) MCASP0_AXR1.ECAP1_IN_APWM_OUT */
		>;
	};

	main_ecap2_pins_default: main-ecap2-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (F24) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */
		>;
	};
};

&main_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	typec_pd0: usb-power-controller@3f {
		compatible = "ti,tps6598x";
		reg = <0x3f>;

		connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			self-powered;
			data-role = "dual";
			power-role = "sink";
			port {
				usb_con_hs: endpoint {
				remote-endpoint = <&usb0_hs_ep>;
				};
			};
		};
	};
};

&main_i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <100000>;
	bootph-all;

	tlv320aic3106: audio-codec@1b {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x1b>;
		ai3x-micbias-vg = <1>;  /* 2.0V */
	};

	exp1: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "OLDI_INT#", "x8_NAND_DETECT",
				   "UART1_FET_SEL", "MMC1_SD_EN",
				   "VPP_EN", "EXP_PS_3V3_EN",
				   "UART1_FET_BUF_EN", "EXP_HAT_DETECT",
				   "DSI_GPIO0", "DSI_GPIO1",
				   "OLDI_EDID", "BT_UART_WAKE_SOC_3V3",
				   "USB_TYPEA_OC_INDICATION", "CSI_GPIO0",
				   "CSI_GPIO1", "WLAN_ALERTn",
				   "HDMI_INTn", "TEST_GPIO2",
				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
				   "MCASP1_FET_SEL", "DSI_EDID",
				   "PD_I2C_IRQ", "IO_EXP_TEST_LED";

		interrupt-parent = <&main_gpio1>;
		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		pinctrl-names = "default";
		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
		bootph-all;
	};

	exp2: gpio@23 {
		compatible = "ti,tca6424";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "BT_EN_SOC", "EXP_PS_5V0_EN",
				   "", "",
				   "", "",
				   "", "",
				   "WL_LT_EN", "",
				   "TP3", "TP6",
				   "TP4", "TP7",
				   "TP5", "TP8",
				   "SoC_I2C2_MCAN_SEL", "GPIO_HDMI_RSTn",
				   "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
				   "GPIO_OLDI_RSTn", "GPIO_AUD_RSTn",
				   "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST";
	};

	sii9022: bridge-hdmi@3b {
		compatible = "sil,sii9022";
		reg = <0x3b>;
		interrupt-parent = <&exp1>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		#sound-dai-cells = <0>;
		sil,i2s-data-lanes = < 0 >;

		hdmi_tx_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/*
			 * HDMI can be serviced with 3 potential VPs -
			 * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1).
			 * For now, we will service it with DSS0 VP1.
			 */
			port@0 {
				reg = <0>;

				sii9022_in: endpoint {
					remote-endpoint = <&dss0_dpi1_out>;
				};
			};

			port@1 {
				reg = <1>;

				sii9022_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};
};

&main_i2c2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <400000>;
};

&vpu {
	ti,dma-heap-name = "carveout_video";
};

&sdhci0 {
	status = "okay";
	ti,driver-strength-ohm = <50>;
	disable-wp;
	bootph-all;
};

&sdhci1 {
	/* SD/MMC */
	status = "okay";
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vddshv_sdio>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	disable-wp;
	bootph-all;
};

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&main_rgmii1_pins_default>,
		    <&main_rgmii2_pins_default>;
	status = "okay";
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy0>;
	status = "okay";
};

&cpsw_port2 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy1>;
	status = "okay";
};

&cpsw3g_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mdio1_pins_default>;
	status = "okay";

	cpsw3g_phy0: ethernet-phy@0 {
		reg = <0>;
		bootph-all;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};

	cpsw3g_phy1: ethernet-phy@1 {
		reg = <1>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&usbss0 {
	status = "okay";
	ti,vbus-divider;
};

&usbss1 {
	status = "okay";
	ti,vbus-divider;
};

&usb0 {
	usb-role-switch;

	port {
		usb0_hs_ep: endpoint {
			remote-endpoint = <&usb_con_hs>;
		};
	};
};

&usb1 {
	dr_mode = "host";
	pinctrl-names = "default";
	pinctrl-0 = <&main_usb1_pins_default>;
};

&mcasp1 {
	status = "okay";
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&main_mcasp1_pins_default>;

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;

	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
	       1 0 2 0
	       0 0 0 0
	       0 0 0 0
	       0 0 0 0
	>;
};

&fss {
	bootph-all;
};

&ospi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;
	bootph-all;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		cdns,phy-mode;
		bootph-all;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			bootph-all;

			partition@0 {
				label = "ospi.tiboot3";
				reg = <0x00 0x80000>;
			};

			partition@80000 {
				label = "ospi.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "ospi.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "ospi.env";
				reg = <0x680000 0x40000>;
			};

			partition@6c0000 {
				label = "ospi.env.backup";
				reg = <0x6c0000 0x40000>;
			};

			partition@800000 {
				label = "ospi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fc0000 {
				label = "ospi.phypattern";
				reg = <0x3fc0000 0x40000>;
				bootph-all;
			};
		};
	};
};

&mailbox0_cluster0 {
	status = "okay";

	mbox_r5_0: mbox-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster1 {
	status = "okay";

	mbox_mcu_r5_0: mbox-mcu-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&wkup_r5fss0 {
	status = "okay";
};

&wkup_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
			<&wkup_r5fss0_core0_memory_region>;
};

&mcu_r5fss0 {
	status = "okay";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	interrupts-extended = <&gic500 GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
			<&main_pmx0 0x1c8>; /* (D14) UART0_RXD PADCONFIG114 */
	interrupt-names = "irq", "wakeup";
	status = "okay";
	bootph-all;
};

&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
	/* Main UART1 is used by TIFS firmware */
	status = "reserved";
	bootph-all;
};

&mcu_pmx0 {
	bootph-all;

	wkup_uart0_pins_default: wkup-uart0-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
			AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
		>;
		bootph-all;
	};
};

&wkup_uart0 {
	/* WKUP UART0 is used by DM firmware */
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	status = "reserved";
	bootph-all;
};

/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
	status = "reserved";
};

&mcu_gpio_intr {
	status = "reserved";
};

&dss_oldi_io_ctrl {
	bootph-all;
};

&reserved_memory {
       #address-cells = <2>;
       #size-cells = <2>;
       rtos_framebuffer_memory_region: rtos-framebuffer-memory@96000000 {
               reg = <0x00 0x96000000 0x00 0x02000000>;
               no-map;
       };
};

&dss0 {
	bootph-all;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_dpi_pins_default>;
};

&dss0_ports {
	/* DSS0-VP2: DPI/HDMI Output */
	hdmi0_dss: port@1 {
		reg = <1>;

		dss0_dpi1_out: endpoint {
			remote-endpoint = <&sii9022_in>;
		};
	};
};

&epwm0 {
	/* Pin 24/26 of J4 */
	pinctrl-names = "default";
	pinctrl-0 = <&main_epwm0_pins_default>;
	status = "okay";
};

&epwm1 {
	/* Pin 23/19 of J4 */
	pinctrl-names = "default";
	pinctrl-0 = <&main_epwm1_pins_default>;
	status = "okay";
};

&ecap1 {
	/* ECAP1 in APWM mode */
	/* Pin 36 of J4 */
	pinctrl-names = "default";
	pinctrl-0 = <&main_ecap1_pins_default>;
	status = "okay";
};

&ecap2 {
	/* ECAP2 in APWM mode */
	/* Pin 11 of J4 */
	pinctrl-names = "default";
	pinctrl-0 = <&main_ecap2_pins_default>;
	status = "okay";
};

&sdhci2 {
	status = "okay";
	bootph-all;
	vmmc-supply = <&wlan_en>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc2_pins_default>;
	bus-width = <4>;
	non-removable;
	ti,fails-without-test-cd;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,driver-strength-ohm = <50>;

	#address-cells = <1>;
	#size-cells = <0>;
	wifi: cc33xx@2 {
		compatible = "ti,cc3300";
		reg = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_wlirq_pins_default>;
	};
};
&main_pmx0 {
	main_mcan0_pins_default: main-mcan0-pins-default {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */
			AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */
		>;
	};

	main_mcan1_pins_default: main-mcan1-pins-default {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */
			AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */
		>;
	};
};

&mcu_pmx0 {
	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */
			AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */
			AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */
		>;
	};
};

&main_i2c2{
	/*
	* main_i2c2 is using (U25) and (T22)
	* so disable to use main_mcan1
	*/
	status = "disabled";
};

&main_i2c1 {
	/*
	* Unset GPIO SoC_I2C2_MCAN_SEL to
	* route MCAN1 signals to MCAN1 HDR
	*/
	gpio@23 {
		p20-hog {
		/* P20 - SoC_I2C2_MCAN_SEL */
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "SoC_I2C2_MCAN_SEL";
		};
	};
};

&main_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan0_pins_default>;
	phys = <&transceiver1>;
};

&main_mcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan1_pins_default>;
	phys = <&transceiver2>;
};

&mcu_mcan0 {
	status = "reserved";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan0_pins_default>;
	phys = <&transceiver3>;
};

&mcu_mcan1 {
	status = "reserved";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan1_pins_default>;
	phys = <&transceiver4>;
};

overlay:

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/**
 * ITE IT6263 single-link LVDS to HDMI bridge DT overlay for AM62P5-SK
 *
 * Wiring: DSS1 VP1 (DPI0) -> OLDI TX1 (single link, PLL18) -> IT6263 -> HDMI type-A
 *
 * Adapted from the NXP i.MX95 it6263 overlay (imx95-19x19-evk-it6263.dtso)
 * to the TI AM62P DSS/OLDI topology. DSS1 cannot run dual link and its
 * single-link OLDI is capped at 100 MHz, so only modes at or below 100 MHz
 * pixel clock (for example 720p60) will work on this path. DSS0 OLDI is
 * not used by this overlay.
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

&{/} {
	hdmi-connector {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&it6263_out>;
			};
		};
	};
};

/*
 * I2C bus routed to the OLDI/LCD connector on the SK-AM62P (main_i2c1).
 * Adjust the bus and the reset GPIO to match the carrier board wiring.
 * exp1 is the TCA6424 GPIO expander already present on main_i2c1 in
 * k3-am62p5-sk.dts; pick a free line for the bridge reset.
 */
&main_i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;

	lvds-to-hdmi-bridge@4c {
		compatible = "ite,it6263";
		reg = <0x4c>;
		reset-gpios = <&exp2 20 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* Single-link LVDS input from DSS1 OLDI TX1 */
			port@0 {
				reg = <0>;
				data-mapping = "jeida-24";

				it6263_in: endpoint {
					remote-endpoint = <&oldi1_dss1_out>;
				};
			};

			/* HDMI output */
			port@1 {
				reg = <1>;

				it6263_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};
};

&dss1 {
	status = "okay";
	/* mux 235: OLDI TX1 <- DSS1 VP0 + PLL18; 241: PLL18 for DSS1 VP0 */
	assigned-clocks = <&k3_clks 235 7>, <&k3_clks 241 0>;
	assigned-clock-parents = <&k3_clks 235 9>, <&k3_clks 241 1>;
};

/* OLDI TX1 only - single link, DSS1 VP1 with PLL18 */
&oldi1_dss1 {
	status = "okay";
};

&oldi1_dss1_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;

		oldi1_dss1_in: endpoint {
			remote-endpoint = <&dss1_dpi0_out>;
		};
	};

	port@1 {
		reg = <1>;

		oldi1_dss1_out: endpoint {
			remote-endpoint = <&it6263_in>;
		};
	};
};

&dss1_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/* VP1 (VP0 in the AM62P DSS app note): Output to OLDI TX1 */
	port@0 {
		reg = <0>;

		dss1_dpi0_out: endpoint {
			remote-endpoint = <&oldi1_dss1_in>;
		};
	};
};

/*
 * Enabling DSS display sharing 
 * Routes HDMI to WKUP R5 core 
 * Independent VP
 */
&dss0 {
       ti,dss-shared-mode;
       ti,dss-shared-mode-vp = "vp1", "vp2";
       ti,dss-shared-mode-vp-owned = <1>, <0>;
       ti,dss-shared-mode-common = "common1";
       ti,dss-shared-mode-planes = "vid";
       ti,dss-shared-mode-plane-zorder = <0>;
       interrupt-parent = <&gic500>;
       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};

&reserved_memory {
       #address-cells = <2>;
       #size-cells = <2>;
       rtos_framebuffer_memory_region: rtos-framebuffer-memory@96000000 {
               reg = <0x00 0x96000000 0x00 0x02000000>;
               no-map;
       };
};

/*
 * Disable the onboard sii9022 HDMI bridge (DSS0 VP2/DPI1) — this board
 * routes HDMI out via IT6263/OLDI TX0 (VP1/DPI0) instead.
 */
// &sii9022 {
// 	status = "disabled";
// };

// &hdmi0 {
// 	status = "disabled";
// };

// &hdmi0_dss {
// 	status = "disabled";
// };

syscfg :

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM62Px" --part "Default" --package "AMH" --context "wkup-r5fss0-0" --product "MCU-PLUS-SDK-AM62P@11.02.00"
 * @v2CliArgs --device "AM62P" --package "FCBGA (AMH)" --variant "AM62P54-M" --context "wkup-r5fss0-0" --product "MCU-PLUS-SDK-AM62P@11.02.00"
 * @versions {"tool":"1.24.2+4234"}
 */

/**
 * Import the modules used in this configuration.
 */
const flash       = scripting.addModule("/board/flash/flash", {}, false);
const flash1      = flash.addInstance();
const bootloader  = scripting.addModule("/drivers/bootloader/bootloader", {}, false);
const bootloader1 = bootloader.addInstance();
const bootloader2 = bootloader.addInstance();
const bootloader3 = bootloader.addInstance();
const dss         = scripting.addModule("/drivers/dss/dss", {}, false);
const dss1        = dss.addInstance();
const gtc         = scripting.addModule("/drivers/gtc/gtc");
const ipc         = scripting.addModule("/drivers/ipc/ipc");
const mcan        = scripting.addModule("/drivers/mcan/mcan", {}, false);
const mcan1       = mcan.addInstance();
const uart        = scripting.addModule("/drivers/uart/uart", {}, false);
const uart1       = uart.addInstance();
const clock       = scripting.addModule("/kernel/dpl/clock");
const debug_log   = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7   = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71  = mpu_armv7.addInstance();
const mpu_armv72  = mpu_armv7.addInstance();
const mpu_armv73  = mpu_armv7.addInstance();
const mpu_armv74  = mpu_armv7.addInstance();
const mpu_armv75  = mpu_armv7.addInstance();
const mpu_armv76  = mpu_armv7.addInstance();
const mpu_armv77  = mpu_armv7.addInstance();
const mpu_armv78  = mpu_armv7.addInstance();
const mpu_armv79  = mpu_armv7.addInstance();
const mpu_armv710 = mpu_armv7.addInstance();
const mpu_armv711 = mpu_armv7.addInstance();
const mpu_armv712 = mpu_armv7.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
bootloader1.appImageOffset = "0x240000";
bootloader1.$name          = "CONFIG_BOOTLOADER_FLASH_HSM";

bootloader2.$name          = "CONFIG_BOOTLOADER_FLASH_MCU";
bootloader2.appImageOffset = "0x800000";

bootloader3.$name          = "CONFIG_BOOTLOADER_FLASH_LINUX";
bootloader3.appImageOffset = "0x1200000";

bootloader1.flashDriver                                 = flash1;
bootloader2.flashDriver                                 = flash1;
bootloader3.flashDriver                                 = flash1;
flash1.$name                                            = "CONFIG_FLASH_SBL";
flash1.serialFlashDriver.$name                          = "board_flash_serialFlash_serialflash0";
flash1.serialFlashDriver.peripheralDriver.dmaEnable     = true;
flash1.serialFlashDriver.peripheralDriver.phyEnable     = true;
flash1.serialFlashDriver.peripheralDriver.$name         = "CONFIG_OSPI_SBL";
flash1.serialFlashDriver.peripheralDriver.phySkipTuning = true;

dss1.$name                                   = "CONFIG_DSS0";
dss1.backgroundColor                         = 0x0;
dss1.vidlFrameFormat                         = "ARGB32_8888";
dss1.dispShare                               = true;
dss1.selectOverlayManager                    = "OVR2";
dss1.selectVP                                = "VP2";
dss1.selectDisplayInterface                  = "DPI";
dss1.vidlInputFrameheight                    = 720;
dss1.vidlOutputFrameHeight                   = 720;
dss1.pixelClkFreq                            = 100200000;
dss1.panelHeight                             = 720;
dss1.hSyncLength                             = 120;
dss1.vBackPorch                              = 10;
dss1.vFrontPorch                             = 10;
dss1.vSyncLength                             = 16;
dss1.hBackPorch                              = 76;
dss1.hFrontPorch                             = 64;
dss1.DPIPanel[0].$name                       = "CONFIG_PANEL0";
dss1.DPIPanel[0].bridgeSII9022A.$name        = "board_panel_bridge_bridge_sii9022a0";
dss1.DPIPanel[0].i2cInstance.I2C_child.$name = "drivers_i2c_v0_i2c_v0_template0";
dss1.DPIPanel[0].i2cInstance.I2C.$assign     = "I2C1";

ipc.vringAllocationPDK = false;

mcan1.$name            = "CONFIG_MCAN0";
mcan1.MCU_MCAN.$assign = "MCU_MCAN1";

uart1.$name                      = "CONFIG_UART_SBL";
uart1.useWakeupDomainPeripherals = false;
uart1.intrEnable                 = "DISABLE";
uart1.addedByBootloader          = true;
uart1.UART.$assign               = "USART0";

const udma                                           = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1                                          = udma.addInstance({}, false);
udma1.$name                                          = "CONFIG_UDMA0";
udma1.parentName                                     = "MCASP";
flash1.serialFlashDriver.peripheralDriver.udmaDriver = udma1;
bootloader1.udmaDriver                               = udma1;
bootloader2.udmaDriver                               = udma1;
bootloader3.udmaDriver                               = udma1;

const udma_blkcopy_channel                                   = scripting.addModule("/drivers/udma/udma_blkcopy_channel", {}, false);
const udma_blkcopy_channel1                                  = udma_blkcopy_channel.addInstance({}, false);
udma_blkcopy_channel1.$name                                  = "CONFIG_UDMA_BLKCOPY_CH0";
flash1.serialFlashDriver.peripheralDriver.udmaBlkCopyChannel = udma_blkcopy_channel1;
bootloader1.udmaBlkCopyChannel                               = udma_blkcopy_channel1;
bootloader2.udmaBlkCopyChannel                               = udma_blkcopy_channel1;
bootloader3.udmaBlkCopyChannel                               = udma_blkcopy_channel1;

debug_log.enableUartLog      = true;
debug_log.uartTrace          = true;
debug_log.uartLog.intrEnable = "DISABLE";
debug_log.uartLog.$name      = "CONFIG_UART_APP";

mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.$name             = "REGISTER_REGION";

mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv72.size              = 7;
mpu_armv72.$name             = "TCMA_VEC";

mpu_armv73.$name    = "DDR";
mpu_armv73.baseAddr = 0x80000000;
mpu_armv73.size     = 31;

mpu_armv74.baseAddr   = 0x41010000;
mpu_armv74.size       = 15;
mpu_armv74.attributes = "NonCached";
mpu_armv74.$name      = "TCMB";

mpu_armv75.size       = 15;
mpu_armv75.attributes = "NonCached";
mpu_armv75.$name      = "TCMA";

mpu_armv76.baseAddr = 0x43C00000;
mpu_armv76.size     = 18;
mpu_armv76.$name    = "HSM_RAM";

mpu_armv77.$name        = "LINUX_VRING";
mpu_armv77.baseAddr     = 0x9C800000;
mpu_armv77.attributes   = "NonCached";
mpu_armv77.size         = 20;
mpu_armv77.allowExecute = false;

mpu_armv78.attributes   = "NonCached";
mpu_armv78.size         = 20;
mpu_armv78.allowExecute = false;
mpu_armv78.baseAddr     = 0x9C900000;
mpu_armv78.$name        = "RESOURCE_TABLE_AND_TRACE";

mpu_armv79.baseAddr     = 0x9B500000;
mpu_armv79.allowExecute = false;
mpu_armv79.attributes   = "NonCached";
mpu_armv79.$name        = "RTOS_NORTOS_IPC_VRING1";
mpu_armv79.size         = 20;

mpu_armv710.$name        = "RTOS_NORTOS_IPC_VRING2";
mpu_armv710.baseAddr     = 0x9B600000;
mpu_armv710.size         = 21;
mpu_armv710.allowExecute = false;
mpu_armv710.attributes   = "NonCached";

mpu_armv711.$name        = "FSS0_OSPI0_CTRL_REG";
mpu_armv711.baseAddr     = 0xFC40000;
mpu_armv711.size         = 8;
mpu_armv711.attributes   = "Device";
mpu_armv711.allowExecute = false;

mpu_armv712.$name        = "UART0_REG";
mpu_armv712.baseAddr     = 0x2800000;
mpu_armv712.size         = 9;
mpu_armv712.attributes   = "Device";
mpu_armv712.allowExecute = false;

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
flash1.serialFlashDriver.peripheralDriver.OSPI.$suggestSolution      = "OSPI0";
flash1.serialFlashDriver.peripheralDriver.OSPI.CLK.$suggestSolution  = "OSPI0_CLK";
flash1.serialFlashDriver.peripheralDriver.OSPI.CSn0.$suggestSolution = "OSPI0_CSn0";
flash1.serialFlashDriver.peripheralDriver.OSPI.DQS.$suggestSolution  = "OSPI0_DQS";
flash1.serialFlashDriver.peripheralDriver.OSPI.D7.$suggestSolution   = "OSPI0_D7";
flash1.serialFlashDriver.peripheralDriver.OSPI.D6.$suggestSolution   = "OSPI0_D6";
flash1.serialFlashDriver.peripheralDriver.OSPI.D5.$suggestSolution   = "OSPI0_D5";
flash1.serialFlashDriver.peripheralDriver.OSPI.D4.$suggestSolution   = "OSPI0_D4";
flash1.serialFlashDriver.peripheralDriver.OSPI.D3.$suggestSolution   = "OSPI0_D3";
flash1.serialFlashDriver.peripheralDriver.OSPI.D2.$suggestSolution   = "OSPI0_D2";
flash1.serialFlashDriver.peripheralDriver.OSPI.D1.$suggestSolution   = "OSPI0_D1";
flash1.serialFlashDriver.peripheralDriver.OSPI.D0.$suggestSolution   = "OSPI0_D0";
dss1.DSS.$suggestSolution                                            = "DSS0";
dss1.DSS.DATA0.$suggestSolution                                      = "VOUT0_DATA0";
dss1.DSS.DATA1.$suggestSolution                                      = "VOUT0_DATA1";
dss1.DSS.DATA2.$suggestSolution                                      = "VOUT0_DATA2";
dss1.DSS.DATA3.$suggestSolution                                      = "VOUT0_DATA3";
dss1.DSS.DATA4.$suggestSolution                                      = "VOUT0_DATA4";
dss1.DSS.DATA5.$suggestSolution                                      = "VOUT0_DATA5";
dss1.DSS.DATA6.$suggestSolution                                      = "VOUT0_DATA6";
dss1.DSS.DATA7.$suggestSolution                                      = "VOUT0_DATA7";
dss1.DSS.DATA8.$suggestSolution                                      = "VOUT0_DATA8";
dss1.DSS.DATA9.$suggestSolution                                      = "VOUT0_DATA9";
dss1.DSS.DATA10.$suggestSolution                                     = "VOUT0_DATA10";
dss1.DSS.DATA11.$suggestSolution                                     = "VOUT0_DATA11";
dss1.DSS.DATA12.$suggestSolution                                     = "VOUT0_DATA12";
dss1.DSS.DATA13.$suggestSolution                                     = "VOUT0_DATA13";
dss1.DSS.DATA14.$suggestSolution                                     = "VOUT0_DATA14";
dss1.DSS.DATA15.$suggestSolution                                     = "VOUT0_DATA15";
dss1.DSS.DATA16.$suggestSolution                                     = "GPMC0_AD8";
dss1.DSS.DATA17.$suggestSolution                                     = "GPMC0_AD9";
dss1.DSS.DATA18.$suggestSolution                                     = "GPMC0_AD10";
dss1.DSS.DATA19.$suggestSolution                                     = "GPMC0_AD11";
dss1.DSS.DATA20.$suggestSolution                                     = "GPMC0_AD12";
dss1.DSS.DATA21.$suggestSolution                                     = "GPMC0_AD13";
dss1.DSS.DATA22.$suggestSolution                                     = "GPMC0_AD14";
dss1.DSS.DATA23.$suggestSolution                                     = "GPMC0_AD15";
dss1.DSS.DE.$suggestSolution                                         = "VOUT0_DE";
dss1.DSS.EXTPCLKIN.$suggestSolution                                  = "GPMC0_WAIT1";
dss1.DSS.HSYNC.$suggestSolution                                      = "VOUT0_HSYNC";
dss1.DSS.PCLK.$suggestSolution                                       = "VOUT0_PCLK";
dss1.DSS.VSYNC.$suggestSolution                                      = "VOUT0_VSYNC";
dss1.DPIPanel[0].i2cInstance.I2C.SCL.$suggestSolution                = "I2C1_SCL";
dss1.DPIPanel[0].i2cInstance.I2C.SDA.$suggestSolution                = "I2C1_SDA";
mcan1.MCU_MCAN.RX.$suggestSolution                                   = "MCU_MCAN1_RX";
mcan1.MCU_MCAN.TX.$suggestSolution                                   = "MCU_MCAN1_TX";
uart1.UART.RXD.$suggestSolution                                      = "UART0_RXD";
uart1.UART.TXD.$suggestSolution                                      = "UART0_TXD";
debug_log.uartLog.WKUP_UART.$suggestSolution                         = "WKUP_USART0";
debug_log.uartLog.WKUP_UART.RXD.$suggestSolution                     = "WKUP_UART0_RXD";
debug_log.uartLog.WKUP_UART.TXD.$suggestSolution                     = "WKUP_UART0_TXD";

log :

Both displays are listing: 
console:/sys/class/drm # ls
card0  card1  card1-HDMI-A-1  card2  card2-HDMI-A-2  renderD128  version

AM625: Subject: AM62x – Why is TX-DIS (Bit 21) missing from k3-pinctrl.h?

Chetan Biluve — Mon, 09 Nov 2026 10:41:14 GMT

Part Number: AM625

Hi TI Team,

While reviewing the AM62x pad configuration register and Linux device-tree pinctrl definitions, I noticed that bit 21 (TX-DIS) does not appear to have a corresponding macro definition in the following header:

arch/arm64/boot/dts/ti/k3-pinctrl.h

The header provides definitions for several pad configuration fields, including:

Bits 16–18: PULLUDEN, PULLTYPESEL and RXACTIVE
Bits 19–20: Drive strength (DRV_STR)
Bit 21: TX-DIS (not defined)
Bits 24–29: Deep Sleep and wakeup configuration

I would like to understand why TX-DIS (bit 21) is not exposed through the K3 pinctrl device-tree definitions.

Could you please clarify:

Is TX-DIS (bit 21) intentionally excluded from k3-pinctrl.h?
Is this bit supported by the AM62x pad configuration hardware?
Is TX-DIS controlled by another hardware block or Linux subsystem?
If supported, can this functionality be exposed through a device-tree pinctrl macro?

My intention is to understand whether this is an intentional design decision or an omission in the existing K3 pinctrl definitions.

Platform: TI AM62x / AM6204
Kernel: Linux TI K3
File: arch/arm64/boot/dts/ti/k3-pinctrl.h

Thanks for your clarification.

TDA4VH-Q1: JTAG unlock using trace 32 lauterbach script on device running SPL bootloader

Shibi MAnoharan — Mon, 09 Nov 2026 09:41:33 GMT

Part Number: TDA4VH-Q1

Our product runs SPL bootloader (tiboot3.bin, tispl and u-boot) on HS-SE device. Now, we have the requirement to unlock JTAG for R5 application development. I learned form TI documentation and Forum articles that the below section of sec-cfg.yaml file controls the debug unlock behaviour.

sec_dbg_config:

subhdr:

magic: 0x42AF

size: 16

allow_jtag_unlock: 0x5A

allow_wildcard_unlock: 0x5A

allowed_debug_level_rsvd: 0

rsvd: 0

min_cert_rev: 0x0

jtag_unlock_hosts: [0, 0, 0, 0]

with setting allow_jtag_unlock to 0, unlock attempt with certificate signed with correct key results in 0x0000 response which is expected. with setting allow_jtag_unlock to 0x5A, unlock attempt results in response 0xDEADFA17 even with allow_wildcard_unlock set to 0x5A which skips the SOC ID verification. I have used the correct key to gererate the certificate with required fields.

I would like to know

1. If this is the correct process?

2. Are there any other steps to be considered?

I referred Jacinto 7 HS-SE HSM JTAG Unlock With TRACE32 for this.

TDA4VM: Placing the exception vectors external to the R5F & booting for R5F cores

Baby Sarath Sasidharan Nair — Mon, 09 Nov 2026 09:11:08 GMT

Part Number: TDA4VM
Other Parts Discussed in Thread: DRA829

Hello TI experts,

Kindly request your support in below topic.

As mentioned in the section 6.3.3.12 R5FSS Boot Options in the J721E DRA829 Technical reference manual (SPRUIL1D) , it is possible to have the exception vectors external to the R5F T boot from there instead of the booting from the TCM.

How ever the configuration details for this is missing.

Please share details to configure this method of booting the R5F & also share the advantages of this method over booting from TCM.

The project would like to check the feasibilty of this booting method

Thanks

Sarath